3.17.7 SPI operation

When the Routing table is set up, SPIs can be programmed through any connected chip, and accesses to update stored values are routed over the cross-chip interface of the chip that owns the SPIs.

SPIs can be routed to remote chips by programming the relevant GICD_IROUTER register. Remote chips are targeted using either Affinity2 or Affinity3, and the Affinity level can be discovered using GICD_CFGID.AFSL.

If SPIs within a SPI block are sent to multiple chips, Arm recommends that you do not read or write registers GICD_ISACTIVE, GICD_ICACTIVE, GICD_ISPENDR, and GICD_ICPENDR. It is inefficient and these registers are not needed for immediate operation.

You can set interrupts to pending by writing to GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_CLRSPI_SR. For efficient operation, Arm recommends that sources are programmed to write SPI IDs that are owned by their chip. Other SPI IDs are supported if these SPIs are owned somewhere in your system.


By default, the GIC-600 does not guarantee that the pending bit has reached the point of serialization for writes to set interrupts pending. This means that there is a race between the pending bit being set and an activate being processed by the GIC after the bresp signal is asserted. To ensure that writes are always propagated to the point of serialization, write 1 to GICD_FCTLR.POS.

SPIs and the Collator

The SPI Collator wires are always connected to the lowest owned SPIs on the chip. If GICD_CHIPRn.SPI_BLOCK_MIN = 4, the SPI Collator wires to chip x drive SPI IDs that start from 160, calculated by (4 × 32) + 32 = 160.

Therefore, in a homogeneous two-chip system, each chip must not use more wires than 16 × (the number of configured SPI blocks).

SPI 1 of N

The GIC-600 never sends a 1 of N SPI to another chip.

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