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Multichip operation mainly affects the behavior of SPIs.
Systems that comprise more than one chip can have several SoCs that are connected externally, or a SoC comprising several SoCs connected inside a single physical package. In all cases, each SoC is integrated with a GIC-600. A multichip system can have up to 16 chips.
PPIs do not require any specific multichip consideration because they are confined to a single core, and programming occurs through the associated GICR register space on the same chip as the core. SGIs behave the same in multichip and single chip configurations where all addressing is through MPIDR values.
To control the consistency of all chips in the configuration, the GIC-600 uses a set of registers that define the connectivity between chips. These registers are referred to as the Routing table and consist of three register types:
GICD_CHIPRn defines the Routing table. It specifies the SPIs that the chip owns, and how the chip is accessed. This register exists on each chip in the multichip configuration so that each chip has a copy of the Routing table. The register number <n> corresponds to its chip_ID.
GICD_DCHIPR specifies the current chip that is responsible for the consistency of the Routing table, and indicates when an update is in progress. A single copy of this register exists on each chip in the multichip configuration.
GICD_CHIPSR specifies details of the current status of the chip. A single copy of this register exists on each chip in the multichip configuration.
At reset, each chip in the multichip system configuration is effectively a standalone full-featured GIC. The GICD_CHIPSR register on the chip indicates this state with bit RTS == Disconnected.
For the multichip configuration to be fully coherent, all chips in the configuration must be interconnected and one chip must own the Routing table.
The sequence for connecting chips together is described in 3.17.2 Connecting the chips.
When multiple chips in the configuration are connected, each set of 32 SPIs (SPI block) is owned by a specific chip, so that the SPI space between chips is partitioned.
SPI wires on a chip can only be used for SPIs that are owned. However, message-based accesses to SPIs owned on any chip are supported.