4.9.2 Event Type Configuration Registers, GICP_EVTYPERn

These registers configure which events are counted by the event counter n. The GIC-600 supports five counters, n = 0-4.

The GICP_EVTYPERn characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all GIC-600 configurations.
AttributesSee 4.9 GICP register summary.

The following figure shows the bit assignments.

Figure 4-44 GICP_EVTYPERn bit assignments
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The following table shows the bit assignments.

Table 4-59 GICP_EVTYPERn bit assignments

Bits Name Function

When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set.

[30:18] - Reserved.
[17:16] EVENT_TYPE

Event tracking type:

0b00 = Count events.

0b10 = MaximumEvent.

0b11 = Reserved.

[15:8] - Reserved.
[7:0] EVENT

Event identifier.

All events reset to an unknown value.

Registers corresponding to unimplemented counters are RES0.

See Table   4-60 EVENT field encoding.

The following table shows the events that the GIC can count.

Table 4-60 EVENT field encoding

Event Description EventID Filter
CLK Clock cycle. 0x0 None
CLK_NG Clock cycle that prevents Q-Channel clock gating. 0x1 None
- Reserved. 0x2-0x3 -
DN_MSG Downstream message to core excluding PPIs. 0x4 Target
DN_SET Set to core SPIs and LPIs. 0x5 Target/ID range
DN_SET1OFN Set to core, which is a 1 of N interrupts. 0x6 Target/ID range
- Reserved. 0x7 -
UP_MSG Upstream message from core. 0x8 Target
UP_ACT Upstream Activate. 0x9 Target/ID range
UP_REL Upstream Release. 0xA Target/ID range
UP_ACTREL Upstream Activate or Release. 0xB Target/ID range
UP_SET_COMP A Set followed by Activate. This counts the set and then decrements on Release. 0xC Target/ID range
UP_DEACT Upstream Deactivate. SPIs only. 0xD Target/ID range
SGI_BRD Broadcast SGI messages. Target = source. 0x10 Target/ID range
SGI_TAR Targeted SGI messages. Target = source. 0x11 Target/ID range
SGI_ALL All SGI messages. Target = source. 0x12 Target/ID range
SGI_ACC Accepted SGI. Target = source. 0x13 Target/ID range
SGI_BRD_CC_IN Broadcast SGI message from cross-chip. 0x14 ID range
SGI_TAR_CC_IN Targeted SGI Message from cross-chip. 0x15 ID range
SGI_TAR_CC_OUT Targeted SGI sent cross-chip. 0x16 Chip/ID range
ITS_NLL_LPI Incoming LPI. 0x20 Target/ID range/ITS
ITS_LL_LPI Incoming low latency LPI. 0x21 Target/ID range/ITS
ITS_LPI Incoming LPI (or low latency). 0x22 Target/ID range/ITS
ITS_LPI_CMD Incoming LPI command. 0x23 Target/ID range/ITS
ITS_DID_MISS Number of DeviceID cache misses. 0x24 Target/ID range/ITS
ITS_VID_MISS Number of EventID cache misses. 0x25 Target/ID range/ITS
ITS_COL_MISS Number of Collection cache misses. 0x26 Target/ID range/ITS
ITS_LAT Latency of the ITS transaction. 0x27 Target/ID range/ITS
ITS_MPFA Number of free slots during translation. 0x28 Target/ID range/ITS
LPI_CC_OUT LPI sent cross-chip. 0x29 ID range/Chip
LPI_CMD_CC_OUT LPI command sent cross-chip. 0x2A ID range/Chip
LPI_CC_IN LPI coming in from cross-chip. 0x2B Target/ID range/Chip
LPI_CMD_CC_IN LPI command coming in from cross-chip. 0x2C Target/ID range/Chip
LPI_OWN_STORED LPI stored in own location. 0x30 -
LPI_OOL_STORED LPI stored out of location. 0x31 -
LPI_HIT_EN LPI property read cache hit enabled. Uses the filter from counter 0 only. 0x32 Target/ID range
LPI_HIT_DIS LPI property read cache hit disabled. Uses the filter from counter 0 only. 0x33 Target/ID range
LPI_HIT LPI property read cache hit. Uses the filter from counter 0 only. 0x34 Target/ID range
LPI_MATCH LPI coalesced. Uses the filter from counter 0 only. 0x35 Target/ID range
LPI_FAS Number of slots free on new LPI. 0x36 None
LPI_PROP_EN Enabled LPI property fetch. Uses the filter from counter 0. 0x37 Target/ID range
LPI_PROP_DIS Disabled LPI property fetch. Uses the filter from counter 0. 0x38 Target/ID range
LPI_PROP LPI property fetch. Uses the filter from counter 0. 0x39 Target/ID range

Indicates that an LPI has completed.

Uses the filter from counter 0.

0x3A Target/ID range
SPI_COL_MSG New message from SPI Collator. 0x50 ID range
SPI_ENABLED SPI enabled (new SPI or register access if pending). 0x51 ID range
SPI_DISABLED SPI disabled (new SPI that is disabled or register access if pending). 0x52 ID range
SPI_PENDING_SET New SPI pending valid. 0x53 ID range
SPI_PENDING_CLR SPI pending bit cleared. 0x54 ID range

Collated edge-based SPI. Excludes collation in the collator.

0x55 ID range

SPI from remote chip.

0x57 ID range

SPI sent to remote chip.

0x58 ID range

SPI deactivate message sent.

0x5A ID range
PT_IN_EN Enabled interrupt written to Pending table. 0x60 Target/ID range
PT_IN_DIS Disabled interrupt written to Pending table. 0x61 Target/ID range
PT_PRI Priority of interrupt written to Pending table. 0x62 Target/ID range
PT_IN Interrupt written to Pending table. 0x63 Target/ID range
PT_MATCH Interrupt already set in Pending table. 0x64 Target/ID range
PT_OUT_EN Enabled interrupt taken out of Pending table (also covered PT_MATCH when enabled). 0x65 Target/ID range
PT_OUT_DIS Disabled interrupt taken out of Pending table (also covered PT_MATCH when disabled). 0x66 Target/ID range
PT_OUT Disabled interrupt taken out of Pending table (also covered PT_MATCH). 0x67 Target/ID range
PT_BLOCK_SENT_CC Pending table block that is sent as part of MOVALL. 0x68 None
SPI_CC_LATENCY SPIs outstanding. 0x70 Chip
SPI_CC_LAT_WAIT SPIs waiting to be sent. 0x71 Chip
LPI_CC_LATENCY LPIs outstanding. 0x72 Chip
LPI_CC_LAT_WAIT LPI waiting to be sent. 0x73 Chip
SGI_CC_LATENCY SGIs outstanding. 0x74 Chip
SGI_LAT_WAIT SGIs waiting to be sent. 0x75 Chip
ACC Counter(n − 1) − Counter(n − 2) every cycle. Prevents clock gating. 0x80 None
OFLOW Overflow of Counter n − 1. 0x81 None
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