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The register map is separated into several pages.
The register map pages are defined in the following table.
Table 4-1 Register map pages
|0||GICD||GICD main page.|
|1||GICA||GICD message-based interrupts alias.|
|2||GICT||GIC trace and debug page.|
|4 + (ITSnum × 2)||GITSn||
ITS address page.
Note:ITSnum is the serial number of each ITS, which is from 0 to ITScount-1.
|5 + (ITSnum × 2)||GITSn translate||ITS translation page.|
|4 + (2 × ITScount) + (RDnum × 2)||GICR (LPI)||GICR LPI registers.
Note:ITScount is the total number of ITS.
|5 + (2 × ITScount) + (RDnum × 2)||GICR (SGI)||GICR PPI + SGI registers.
Note:RDnum is the serial number of each “internal Redistributor”, which is from 0 o RDcount-1.
|4 + (2 × ITScount) + (RDcount × 2)||GICDA||Alias to GICD (page after last GICR page).
Note:RDcount is the total number of “internal Redistributor”, which equals total number of CPU cores.
For more information, see Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0.