3.16.6 Error handling records

The GIC-600 has several error records. The range of error handling records that are available depends on the configuration of the GIC-600.

The GIC-600 error handling records are listed in the following table.

Table 3-7 Error handling records

Record Description
0

Uncorrected software error in the Distributor.

Table   3-8 Software errors, record 0

1

Corrected SPI RAM error.

Table   3-9 SPI RAM errors, records 1-2

2

Uncorrected SPI RAM error.

Table   3-9 SPI RAM errors, records 1-2

3

Corrected SGI RAM error.

Table   3-10 SGI RAM errors, records 3-4

4

Uncorrected SGI RAM error.

Table   3-10 SGI RAM errors, records 3-4

5 Reserved.
6 Reserved.
7

Corrected PPI RAM error.

Table   3-11 PPI RAM errors, records 7-8

8

Uncorrected PPI RAM error.

Table   3-11 PPI RAM errors, records 7-8

9

Corrected LPI RAM error. Not present if there is no LPI support.

Table   3-12 LPI RAM errors, records 9-10

10

Uncorrected LPI RAM error. Not present if there is no LPI support.

Table   3-12 LPI RAM errors, records 9-10

11

Corrected error from ITS RAM. Not present if an ITS is not present.

Table   3-13 ITS RAM errors, records 11-12

12

Uncorrected error from ITS RAM. Not present if an ITS is not present.

Table   3-13 ITS RAM errors, records 11-12

13+

Uncorrected software error in ITS. One record per ITS on the chip. Not present if an ITS is not present.

Table   3-15 ITS command and translation errors, records 13+

The details, events, and recovery sequences of each record are described in Software error record 0 to ITS command and translation error records 13+.

Software error record 0

Software error record 0 records software errors that are uncorrectable.

Record 0 contains software programming errors from a wide range of sources within the GIC-600. In general, these errors are contained. For uncorrected errors, the information that is provided gives enough information to enable recovery without significant loss of functionality.

Arm recommends that record 0 is connected to a high priority interrupt. This prevents the record from overflowing if it receives more errors than it is able to process with the possible loss of information required for recovery. See 3.16.5 Error recovery and fault handling interrupts for more information.

The following table describes the syndromes that are recorded in record 0, the reported information, and recovery instructions.

Table 3-8 Software errors, record 0

GICT_ERR<n>STATUS.IERR (Syndrome) GICT_ERR<n>STATUS.SERR

GICT_ERR<n>MISC0.Data

Description (other bits RES0)a

Recovery, Prevention

0x0, SYN_ACE_BAD

Illegal ACE-Lite Slave Access.

0xE

AccessRnW, bit[12]

AccessSparse, bit[11]

AccessSize, bits[10:8]

AccessLength, bits[7:0]

Repeat illegal access, with appropriate size and properties.

Full access address is given in GICT_ERR0ADDR.

0x1, SYN_PPI_PWRDWN

Attempt to access a powered down Redistributor.

0xF

Redistributor, bits[24:16]

Core, bits[8:0]

Ensure that the Redistributor is powered up before accessing. See GICR_PWRR.

Attempt was made by the core reported in MISC0.

0x2, SYN_PPI_PWRCHANGE

Attempt to power down Redistributor rejected.

0xF

Redistributor, bits[24:16]

Core, bits[8:0]

Ensure that the core accessing the register, or all cores with the same GICR_PWRR.RDG if GICR_PWRR.RDAG is set, has completed the GICR_WAKER.ProcessorSleep handshake.

0x3, SYN_GICR_ARE

Attempt to access GICR or GICD registers in mode that cannot work.

0xF Core, bits[8:0] Repeat the access to the specified core accessing the correct register space. That is, if ARE_S and ARE_NS == 1 then PPI and SGI registers must be accessed through the GICRx instead of GICD register space.

0x4, SYN_PROPBASE_ACC

Attempt to reprogram PROPBASE registers to a value that is not accepted because another value is already in use.

0xF Core, bits[8:0]

GICR_PROPBASER is shared between all cores on a chip. When any GICR_CTLR.Enable_LPIs bit is set, the value is locked and cannot be updated unless a complete GICR_WAKER.Sleep handshake is complete.

See A.2 Power control signals.

0x5, SYN_PENDBASE_ACC

Attempt to reprogram PENDBASE registers to a value that is not accepted because another value is already in use.

0xF Core, bits[8:0]

When any GICR_CTLR.Enable_LPIs bit is set, the Shareability, InnerCache, and OuterCache fields are locked for the whole chip. They can only be changed by completing the GICR_WAKER.Sleep handshake.

See A.2 Power control signals. Otherwise, repeat the register access using the current global values.

0x6, SYN_LPI_CLR

Attempt to reprogram ENABLE_LPI when not enabled and not asleep.

0xF Core, bits[8:0]

Arm recommends that you do not clear the Enable_LPIs bit. Instead, interrupts must be unmapped using an ITS. If you must clear, then you must flush the LPI cache using the GICR_WAKER.Sleep handshake.

See A.2 Power control signals.

0x7, SYN_WAKER_CHANGE

Attempt to change GICR_WAKER abandoned due to handshake rules.

0xF Core, bits[8:0] GICR_WAKER.ProcessorSleep and GICR_WAKER.ChildrenAsleep form a four-phase handshake. The attempt to change state must be repeated when the previous transition has completed.

0x8, SYN_SLEEP_FAIL

Attempt to put GIC to sleep failed as cores are not fully asleep.

0xF Core, bits[8:0] All cores must be asleep, using the GICR_WAKER.ProcessorSleep handshake, before you flush the LPI cache using GICR_WAKER.Sleep.

0x9, SYN_PGE_ON_QUIESCE

Core put to sleep before its Group enables were cleared.

0xF Core, bits[8:0] The core must disable its group enables before it toggles the GICR_WAKER.ProcessorSleep handshake, otherwise, the GIC clears its record of the group enables, causing a mismatch between the GIC and the core.

0xA, SYN_GICD_CTLR

Attempt to update GICD_CTLR was prevented due to Register Write Pending (RWP) or Group enable restrictions.

0xF Data, bits[7:0] Software must wait for GICD_CTLR.RWP to be 0 before repeating the GICD_CTLR Write. The data represents the target value.

0x10, SYN_SGI_NO_TGT

SGI sent with no valid destinations.

0xE Core, bits[8:0]

If the SGI is required, software must repeat the SGI from the reported core with a valid target list.

If this level of RAS functionality is required, the software must track generated SGIs externally.

0x11, SYN_SGI_CORRUPTED

SGI corrupted without effect.

0x6 Core, bits[8:0] An SGI is corrupted due to a RAM error in the PPI RAM. The RAM error details are reported separately in record 8. The GIC ignores the SGI generated from the recorded core. If you want software to recover from this, it must use an external record of the generated SGI.

0x12, SYN_GICR_CORRUPTED

Data was read from GICR register space that has encountered an uncorrectable error.

0x6 GICT_ERR0ADDR is populated Software has tried to read corrupted data stored in SGI RAM or PPI RAM. Check records 4 and 8, and perform a recovery sequence for those interrupts.

0x13, SYN_GICD_CORRUPTED

Data was read from GICD register space that encountered an uncorrectable error.

0x6 GICT_ERR0ADDR is populated

Software has tried to read corrupted data stored in SPI RAM.

Check record 2 and perform a recovery sequence for those interrupts.

0x14, SYN_ITS_OFF

Data was read from an ITS that is powered down.

0xF GICT_ERR0ADDR is populated Ensure that the qreqn_its<x> power control Q‑Channel is in the RUN state before accessing the relevant ITS.

0x18, SYN_SPI_BLOCK

Attempt to access a SPI block that is not implemented.

0xE Block, bits[4:0]

No recovery required.

Correct the software.

0x19, SYN_SPI_OOR

Attempt to access a non-implemented SPI using (SET|CLR)SPI.

0xE ID, bits[9:0] Reprogram the issuing device to send a supported SPI ID.

0x1A, SYN_SPI_NO_DEST_TGT

A SPI has no legal target destinations.

0xF ID, bits[9:0] Before enabling the specified SPI, reprogram the SPI to target an existing core.

Note:

The same SPI might repeat this error several times and cause an overflow.

0x1B, SYN_SPI_NO_DEST_1OFN

A 1 of N SPI cannot be delivered due to bad DPG/GICR_CLASS programming.

0xF ID, bits[9:0] Ensure that there is at least one valid target for the specified 1 of N interrupt, that is, ensure that at least one core has acceptable DPG and CLASS settings to enable delivery.

Note:

The same SPI might repeat this error several times and cause an overflow.

0x1C, SYN_COL_OOR

A collator message is received for a non-implemented SPI, or is larger than the number of owned SPIs in a multichip configuration.

0xF ID, bits[9:0] In a multichip configuration, ensure that there are enough owned SPIs to support all SPI wires that are used. Any unsupported interrupts must be disabled at the source.

0x1D, SYN_DEACT_IN

A Deactivate to a non-existent SPI, or with incorrect groups set. Deactivates to LPI and non-existent PPI are not reported.

0xE None A Deactivate occurred to a non-existent SPI, or that SPI group prevented the Deactivate occurring. Software must check the active states of SPIs.

0x1E, SYN_SPI_CHIP_OFFLINE

An attempt was made to send a SPI to an offline chip.

0xF ID, bits[9:0] Software must disable or retarget interrupts that are targeted at offline cores.

0x28, SYN_ITS_REG_SET_OOR

An attempt was made to set an Out-of-Range (OOR) interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16]

Data, bits[15:0]

Software must reprogram the source device to only create legal LPI IDs.

0x29, SYN_ITS_REG_CLR _OOR

An attempt was made to clear an OOR interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16]

Data, bits[15:0]

Software must not attempt to clear non-existent LPIs.

0x2A, SYN_ITS_REG_INV_OOR

An attempt was made to invalidate an OOR interrupt. Only valid when GICR LPI injection registers are supported.

0xE

Core, bits[24:16]

Data, bits[15:0]

Software must not attempt to clear non-existent LPIs.

0x2B, SYN_ITS_REG_SET_ENB

An attempt was made to set an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16]

Data, bits[15:0]

Software must follow architectural steps to enable LPIs on the specified core before enabling the core to send interrupts.

0x2C, SYN_ITS_REG_CLR _ENB

An attempt was made to clear an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16]

Data, bits[15:0]

Software must not try to clear LPIs on a core that does not have LPIs enabled using GICR_CTLR.Enable_LPIs.

0x2D, SYN_ITS_REG_INV_ENB

An attempt was made to invalidate an interrupt when LPIs are not enabled. Only valid when GICR LPI injection registers are supported.

0xF

Core, bits[24:16]

Data, bits[15:0]

Software must not try to invalidate LPIs on a core that does not have LPIs enabled using GICR_CTLR.Enable_LPIs.

0x40, SYN_LPI_PROP_READ_FAIL

An attempt was made to read properties for a single interrupt, where an error response was received with the data.

0x12

Target, bits[31:16]

ID, bits[15:0]

Software must reprogram the LPI Property table for the specified ID with error-free data and then issue an INV command through the ITS. If an overflow occurred, an INVALL command must be issued to all cores.

0x41, SYN_PT_PROP_READ_FAIL

An attempt was made to read properties for a block of interrupts, where an error response was received with the data.

0x12

Target, bits[31:16]

ID, bits[15:0]

Software must reprogram the LPI Property table for the specified ID with error-free data and then issue an INV command through the ITS. If an overflow occurred, an INVALL command must be issued to all cores.

0x42, SYN_PT_COARSE_MAP_READ_FAIL

An attempt was made to read the coarse map for a target, where an error response was received with the data.

0x12

Target, bits[31:16]

No recovery is necessary because the GIC assumes that the coarse map is full.

0x43, SYN_PT_COARSE_MAP_WRITE_FAIL

An attempt was made to write the coarse map for a target, with an error received with the Write response.

0x12

Target, bits[31:16]

The GIC attempts to continue, however this error indicates issues with the memory system, and operation might be unpredictable.

0x44, SYN_PT_TABLE_READ_FAIL

An attempt was made to read a block of interrupts from a Pending table, where an error response was received with the data.

0x12

Target, bits[31:16]

ID, bits[15:0]

Software must determine the reason for the pending error Read fail. The GIC uses the data supplied, however, it is possible for the LPI interrupt to be lost around the specified LPI.

0x45, SYN_PT_TABLE_WRITE_FAIL

An attempt was made to write-back a block of interrupts from a Pending table, with an error received with the write response.

0x12

Target, bits[31:16]

ID, bits[15:0]

The GIC tries to continue, however, this error indicates issues with the memory system, and operation might be unpredictable.

0x46, SYN_PT_SUB_TABLE_READ_FAIL

An attempt was made to read a sub-block of interrupts from a Pending table, where an error response was received with the data.

0x12

Target, bits[31:16]

ID, bits[15:0]

Software must determine the reason for the pending error read fail. The GIC uses the data supplied, however, it is possible for the LPI interrupt to be lost around the specified LPI.

0x47, SYN_PT_TABLE_WRITE_FAIL_BYTE

An attempt was made to write-back a sub-block of interrupts from a Pending table, with an error received with the write response.

0x12

Target, bits[31:16]

ID, bits[15:0]

The GIC tries to continue, however, this error indicates issues with the memory system, and operation might be unpredictable.

SPI RAM error records 1-2

SPI RAM error record 1 records RAM ECC errors that are correctable. SPI RAM error record 2 records RAM ECC errors that are uncorrectable.

SPI RAM error records 1-2 are present if SPI RAM ECC is configured.

The GIC-600 has two SPI RAM, SPI0 and SPI1 that contain the programming for SPIs. SPI0 contains SPIs that have even-numbered IDs, and SPI1 contains SPIs that have odd-numbered IDs.

If a correctable error is detected in SPI RAM, it is corrected and the error is reported in error record 1. See 3.16.5 Error recovery and fault handling interrupts for information about the error counters and interrupt generation options.

Correctable errors do not require software to take any action within the GIC. However, software can choose to track error locations in case a RAM row or column can be repaired, and the RAM has repair capability.

The GICT_ERR1MISC0 reports data for SPI error records 1-2 shown in the following table.

Table 3-9 SPI RAM errors, records 1-2

Record GICT_ERR1MISC0.Data
1 = Correctable Bit location, ID, bits[log2(SPIs)+]
2 = Uncorrectable ID, bits[log2(SPIs) − 1:0]

The RAM address can be determined from the ID >> 1. ID[0] specifies the SPI RAM number.

If a SPI has an uncorrectable error, GICD_IERRRn identifies the SPI. While in this error state, the interrupt reverts to a disabled, Secure group 0, edge-triggered SPI, and Non-secure access is controlled by GICD_FCTLR.NSACR. This enables Secure software to control whether Non-secure accesses can set the interrupt to pending while in the errored state.

For uncorrectable errors, software is required to perform the following recovery sequence:

  1. Read the error record, to determine if an uncorrectable error has occurred.
  2. Clear the error record, to enable future errors to be tracked.
  3. Read all GICD_IERRRn registers, so that you can identify the SPIs that have errors. The GICD_IERRRn registers must be read from the Secure side.

    If the error record reports only one error, the block that contains the error can be determined using the ID in the GICT_ERR2MISC0 register, by calculating the block number as 1 + (ID / 32). However, in the case of an overflow, all GICD_IERRRn registers must be checked.

  4. If necessary, read out any of the current programmed states. This includes programmed data that is corrupted and generates an error, unless GICT_ERR0CTRL.UE is disabled. Arm recommends that intended programming is stored in memory so that this step is not required.
  5. Write to GICD_ICENABLERn, to disable all interrupts that have errors.
  6. Write 1 to the GICD_IERRRn bits that step 3 indicates are showing an SPI error. This write clears the interrupt error and reverts the corresponding GICD_IGROUPRn, GICD_IGRPMODRn, GICD_ICFGRn, and GICD_NSACRn bits to their default values.
  7. Read GICD_IERRRn, to check that the error has cleared. If the error remains, then clear all the GICD_CTLR group enables so that it forces all SPIs to return to their owner chips. When GICD_CTLR.RWP returns to 0, repeat the write to GICD_IERRRn. When the error clear is accepted, you can re-enable the group enables.
  8. Reprogram the interrupt to the intended settings.
  9. If the interrupt is reprogrammed to be level-sensitive, write to GICD_ICPENDRn to ensure that any edge-sensitive pending bits are cleared.
  10. If the interrupt is edge-triggered, Arm recommends that software checks the device, if possible, in case an edge is lost.
  11. Ensure that the active bit is set correctly depending on whether it is being processed. Clear the active bit using GICD_ICACTIVE to ensure that the interrupt is delivered when it is set to pending in the future. However, if the interrupt is being processed in a core, the interrupt might be delivered again before it is deactivated.
  12. Re-enable the reprogrammed interrupts by writing to GICD_ISENABLER.
  13. Recheck the error record, to ensure that no more errors are reported. If necessary, repeat step 2.

SGI RAM error records 3-4

SGI RAM error record 3 records RAM ECC errors that are correctable. SGI RAM error record 4 records RAM ECC errors that are uncorrectable.

SGI RAM error records 3-4 are present if SGI RAM ECC is configured.

The Distributor records a subset of the SGI programming, and stores this information in the SGI RAM, to ensure that it can make the correct routing decisions for SGIs.

If a correctable error is detected in SGI RAM, the error is corrected and the error is reported in error record 3. See 3.16.5 Error recovery and fault handling interrupts for information about the error counters and interrupt generation options.

Correctable errors do not require software to take any action within the GIC. However, the GIC can choose to track error locations in case a RAM row or column can be repaired, and the RAM has repair capability.

The GICT_ERR<n>MISC0 reports data for SGI error records 3-4 shown in the following table.

Table 3-10 SGI RAM errors, records 3-4

Record GICT_ERR<n>MISC0.Data
3 = Correctable

Bit location, log2(width).

Address, bits[(ceiling(cores / 16) × 16) − 1:0].

4 = Uncorrectable Address, bits[(ceiling(cores / 16) × 16) − 1:0].

The RAM stores information for the same SGI for up to 16 cores on a single row.

The corrupted SGI number is given by address × 16 on cores (address - (address × 16)) to (address - (address × 16)) + 15.

GICR_SGIDR contains default values for GICR_IGROUPR0, GICR_IGRPMODR0, and GICR_NSACR for each SGI.

When an SGI is in error, the GIC operates using the values that GICR_SGIDR contains.

For uncorrectable errors that occur in either the PPI or SGI RAM, software is required to perform the following recovery sequence:

  1. Read the error record, to determine if an uncorrectable error has occurred.
  2. Clear the error record, to enable future errors to be tracked.
  3. Read all GICR_IERRVR registers, so that you can identify the SGIs and PPIs that have errors. The GICR_IERRVR registers must be read from the Secure side.
  4. If necessary, read out any of the current programmed states. This includes programmed data that is corrupted and generates an error, unless GICT_ERR0CTRL.UE is disabled. Arm recommends that intended programming is stored in memory so that this step is not required.

    The GICR_NSACR is overwritten when an error occurs, so the pre-error value cannot be read back at this stage.

  5. Write to GICR_ICENABLER0, to disable all interrupts that have errors.
  6. Write 1 to the GICR_IERRVR bits that step 3 indicates are showing an SGI or PPI error. This write clears the interrupt error and reverts the corresponding GICR_IGROUPR0, GICR_IGRPMODR0, and GICR_NSACR bits to their default values. The values of PPIs are not changed.
  7. Reprogram the interrupt to the intended settings.
  8. Re-enable the reprogrammed interrupts by writing to the relevant GICR_ISENABLER0.
  9. Recheck the error record, to ensure that no more errors are reported. If necessary, repeat step 2.

PPI RAM error records 7-8

PPI RAM error record 7 records RAM ECC errors that are correctable. PPI RAM error record 8 records RAM ECC errors that are uncorrectable.

PPI RAM error records 7-8 are present if PPI RAM ECC is configured.

Error records 7-8 record the errors from PPI RAM that contain GICR_IGROUPR0, GICR_IGRPMODR0, and GICR_IPRIORITYRn information for PPIs and SGIs. PPI RAM also contains a buffer that stores generated SGIs when backpressure occurs.

The GICT_ERR<n>MISC0 reports data for PPI error records 7-8 shown in the following table.

Table 3-11 PPI RAM errors, records 7-8

Record GICT_ERR<n>MISC0.Data

7 = Correctable

PPI block, bits[18+].

Bit location, bits[17:12].

Offset, bits[11:8].

SGI/Int, bit[7].

Core, bits[6:0].

8 = Uncorrectable

PPI block, bits[12+].

Offset, bits[11:8].

SGI/Int, bit[7].

Core, bits[6:0].

For uncorrectable errors, software must perform the recovery sequence that is described in SGI RAM error records 3-4.

LPI RAM error records 9-10

LPI RAM error record 9 records RAM ECC errors that are correctable. LPI RAM error record 10 records RAM ECC errors that are uncorrectable. Each error generates an LPI interrupt.

LPI RAM error records 9-10 are present if LPI RAM ECC is configured.

Error records 9-10 record errors from the main LPI cache.

The GICT_ERR<n>MISC0 reports data for LPI error records 9-10 shown in the following table.

Table 3-12 LPI RAM errors, records 9-10

Record GICT_ERR<n>MISC0.Data

9 = Correctable

Bit location, bits[15+].

Reserved, bit[14].

Pendingb, bits[13:12]

Reserved, bits[11:10].

Address, bits[9:0].

10 = Uncorrectable

Pending, bits[13:12].

Reserved, bits[11:10].

Address, bits[9:0].

When an uncorrectable error occurs, the data shown in the table is stored and the GICT_ERR10MISC1 register is updated to contain the RAM contents of the corrupted line. The line in RAM is dropped, and any pending interrupts that it might contain are lost.

If required, software can use the data in the GICT_ERR10MISC1 register to check several interrupt sources, such as the corrupted INTID. This ID is never more than two bits away from the recorded ID.

ITS RAM error records 11-12

ITS RAM error record 11 records ITS RAM ECC errors that are correctable. ITS RAM error record 12 records ITS RAM ECC errors that are uncorrectable.

ITS RAM error records 11-12 are present if an ITS is configured.

Error records 11-12 record the errors from ITS RAM.

All ITS tables are memory backed allowing uncorrectable errors to be read from RAM again without software intervention. These records are used for tracking RAM errors and for possible RAM maintenance.

The GICT_ERR<n>MISC0 reports data for ITS RAM error records 11-12 shown in the following table.

Table 3-13 ITS RAM errors, records 11-12

Record GICT_ERR<n>MISC0.Data

11 = Correctable

Bit location, bits[(x + 15)+].

Address, bits[(x + 14)+].

RAM, bits[x + 2:x].

ITS, bits[x - 1:0].

x = log2(ITS).

12 = Uncorrectable

Address, bits[(x + 3)+].

RAM, bits[x + 2:x].

ITS, bits[x - 1:0].

x = log2(ITS).

GICT_ERR<n>MISC0 gives information relating to the corrupted ITS, RAM, and RAM address. The bit location of a correctable error is also given. The ITS RAM encoding is shown in the following table.

Table 3-14 ITS RAM encoding

RAM Record 11 Record 12
0 None None
1 Device cache Device cache
2 Collection cache Collection cache
3 Event cache Event cache
4 - Reserved
5 - Reserved
6 - Reserved
7 - Event cache, locked

ITS command and translation error records 13+

The ITS command and translation error records 13+ record uncorrectable command and translation errors from each configured ITS.

The ITS command and translation error records capture software events so that the operation of software can be tracked.

The ITS command and translation error records capture software events so that the operation of software can be tracked. The software command errors that are captured are uncorrectable errors only, which require software to correct the command to restart.

The GICT_ERR<n>STATUS.IERR field indicates whether an error is either related to the architecture (0) or is implementation defined (1). In both cases, the full 24-bit syndrome is reported in GICT_ERR<n>MISC0. Extra data is reported in GICT_ERR<n>MISC1.

The data that is captured for each ITS software syndrome is shown in the following table.

Table 3-15 ITS command and translation errors, records 13+

Error mnemonic Encoding IERR Stall Mask Description
MOVALL_TGT_OOR 0x10E20 1 0 -

MOVALL from a core that does not exist.

Command is ignored.

MOVALL_DST_TGT_OOR 0x10E21 1 0 -

MOVALL to a core that does not exist.

Command is ignored.

MOVALL_CHIP_OFFLINE_OOR 0x10E22 1 0 -

MOVALL to a chip that is out-of-range, or from a chip that is offline.

Command is ignored.

MOVALL_ENABLE_LPI_OFF 0x10E23 1 0 -

MOVALL from a core where GICR_CTLR.Enable_LPIs is 0.

Command is ignored.

MOVALL_DST_ENABLE_LPI_OFF 0x10E24 1 0 -

MOVALL to a core where GICR_CTLR.Enable_LPIs is 0, or to a destination chip that is offline.

LPIs on MOVALL source are dropped.

INT_PHYSICALID_OOR 0x10326 1 0 -

INT received with a physical ID that is beyond the range that is specified in GICR_PROPBASER.IDbits.

Software must correct mappings.

Interrupt is dropped and ID is reported in GICT_ERR<n>MISC1.

INT_TGT_OOR 0x10320 1 0 -

INT received for a core that does not exist.

Software must correct mappings.

Interrupt is dropped and TGT is reported in GICT_ERR<n>MISC1.

INT_CHIP_OFFLINE_OOR 0x10322 1 0 -

INT received for a chip that is offline.

Software must either correct mappings or take chip online.

Interrupt is dropped and TGT is reported in GICT_ERR<n>MISC1.

INT_LPI_OFF 0x10323 1 0 -

INT received for TGT with GICR_CTLR.Enable_LPIs disabled.

Software must either enable LPI or correct mappings.

TGT is reported in GICT_ERR<n>MISC1.

MAPD_DEVICE_OOR 0x10801 0 1 CEE A MAPD command has tried to map a device with a DeviceID that is outside the supported range, or that is beyond the memory allocated.
MAPD_ITTSIZE_OOR 0x10802 0 1 CEE A command has tried to allocate an ITT table that is larger than the supported EventID size.
MAPC_COLLECTION_OOR 0x10903 0 1 CEE A MAPC command has tried to map a CollectionID that is not supported. See GITS_TYPER.
MAPC_TGT_OOR 0x10920 1 1/0 CEE

A MAPC command has tried to map to a core that does not exist.

If the core is within the maximum range that the ITS supports, the command stalls.

If the command is detected in the destination Distributor, the command is ignored and the core is reported in GICT_ERR<n>MISC1.

Note:

If the value in GICT_ERR<n>MISC1 is 0, the location of the detected error is in the ITS.

CEE applies to errors detected in the ITS only.

MAPC_LPI_OFF 0x10923 1 0 -

A MAPC command has tried to map a collection to a core that does not have LPIs enabled.

Software must correct the mapping, or it must first enable LPIs using GICR_CTLR.Enable_LPIs.

The core is reported in GICT_ERR<n>MISC1.

MAPC_CHIP_OFFLINE_OOR 0x10922 1 0 -

A MAPC command has targeted a core in an offline chip.

Software must correct the mapping or take the target chip online.

MAPI_DEVICE_OOR 0x10B01 0 1 CEE

A MAPI has tried to map a DeviceID that is not supported.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

MAPI_COLLECTION_OOR 0x10B03 0 1 CEE

A MAPI has tried to map to a collection that is not supported.

See GITS_BASER1c, and for information about the supported range, see GITS_TYPER.

MAPI_ID_OOR 0x10B05 0 1 CEE

A MAPI has tried to map to an EventID size that is not supported.

The size that is supported is reported in GITS_TYPER, but might be reduced depending on the MAPD command for the specified DeviceID.

MAPI_UNMAPPED_DEVICE 0x10B04 0 1 CEE A MAPI has tried to map an interrupt to a device that is not mapped.
MAPVI_DEVICE_OOR 0x10A01 0 1 CEE

A MAPVI has tried to map a device supported by the ITS that is out-of-range.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

MAPVI_COLLECTION_OOR 0x10A03 0 1 CEE

A MAPVI has tried to map to a collection that is outside the range that the ITS supports.

See GITS_BASER1c, and for information about the supported range, see GITS_TYPER.

MAPVI_UNMAPPED_DEVICE 0x10A04 0 1 CEE A MAPVI has tried to map an interrupt to a device that is not mapped.
MAPVI_ID_OOR 0x10A05 0 1 CEE A MAPVI has tried to use an EventID that is outside the size that the corresponding MAPD command supports.
MAPVI_PHYSICALID_OOR 0x10A06 0 1 CEE

A MAPVI is received that has a physical ID outside the range supported.

The supported range is >16-<8096 bits.

MOVI_DEVICE_OOR 0x10101 0 1 CEE

A MAPVI has tried to map a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

MOVI_COLLECTION_OOR 0x10103 0 1 CEE

A MOVI has tried to use a collection that is outside the range that the ITS supports.

See GITS_BASER1c, and for information about the supported range, see GITS_TYPER.

MOVI_UNMAPPED_DEVICE 0x10104 0 1 CEE A MOVI has tried to move an interrupt from a device that is not mapped.
MOVI_ID_OOR 0x10105 0 1 CEE A MOVI has tried to use an EventID that is outside the size that the corresponding MAPD command supports.
MOVI_UNMAPPED_INTERRUPT 0x10107 0 1 CEE A MOVI command has tried to operate on an interrupt that is not mapped.
MOVI_UNMAPPED_COLLECTION 0x10109 0 1 CEE A MOVI command has tried to operate on a collection that is not mapped.
DISCARD_DEVICE_OOR 0x10F01 0 1 CEE

A DISCARD has tried to use a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

DISCARD_UNMAPPED_DEVICE 0x10F04 0 1 CEE A DISCARD has tried to drop an interrupt from a device that is not mapped.
DISCARD_ID_OOR 0x10F05 0 1 CEE A DISCARD command has tried to use an EventID that is outside the size that the corresponding MAPD command supports.
DISCARD_UNMAPPED_INTERRUPT 0x10F07 0 1 CEE A MOVI command has tried to operate on an interrupt that is not mapped.
DISCARD_ITE_INVALID 0x10F10 0 1 CEE A MOVI command has tried to operate on an EventID that is not supported by the corresponding MAPD command.
INV_DEVICE_OOR 0x10C01 0 1 CEE

An INV has tried to use a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

INV_UNMAPPED_DEVICE 0x10C04 0 1 CEE An INV has tried to invalidate an interrupt from a device that is not mapped.
INV_ID_OOR 0x10C05 0 1 CEE An INV has tried to use an EventID that is outside the size that the corresponding MAPD command supports.
INV_UNMAPPED_INTERRUPT 0x10C07 0 1 CEE An INV has tried to invalidate an interrupt that is not mapped.
INV_ITE_INVALID 0x10C10 0 1 CEE An INV has tried to invalidate an interrupt with an EventID that is invalid.
INV_PHYSICALID_OOR 0x10C26 1 1 CEE

An INV has tried to invalidate an interrupt with a physical ID that is larger than the target supports.

See GICR_PROPBASER.IDbitsc.

INV_TGT_OOR 0x10C20 1 1 CEE An INV has tried to invalidate an interrupt that is mapped to an invalid target.
INV_LPI_OFF 0x10C23 1 1 CEE

An INV has tried to invalidate an interrupt that is mapped to a target that does not have LPIs enabled.

See GICR_CTLR.Enable_LPIsc.

INV_CHIP_OFFLINE_OOR 0x10C22 1 1 CEE An INV has tried to invalidate an interrupt that is mapped to a chip that is offline.
INVALL_COLLECTION_OOR 0x10D03 0 1 CEE

An INVALL has tried to invalidate an OOR collection. See GITS_TYPER.

INVALL_UNMAPPED_COLLECTION 0x10D09 0 1 CEE An INVALL has tried to invalidate a collection that is not mapped.
INVALL_TGT_OOR 0x10D20 1 1 CEE An INVALL has been sent to an illegal target.
INVALL_LPI_OFF 0x10D23 1 1 CEE An INVALL has been sent to a target that has LPIs turned off.
INVALL_CHIP_OFFLINE_OOR 0x10D22 1 1 CEE An INVALL has tried to invalidate an interrupt from a device that is not mapped.
INT_DEVICE_OOR 0x10301 0 1 UEE

An incoming translation has attempted to use a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

INT_UNMAPPED_DEVICE 0x10304 0 1 UEE An incoming translation has tried to invalidate an interrupt from a device that is not mapped.
INT_ID_OOR 0x10305 0 1 UEE An INT has tried to use an EventID that is outside the size that the corresponding MAPD command supports.
INT_UNMAPPED_INTERRUPT 0x10307 0 1 UEE An INT command has tried to raise an interrupt that is not mapped.
INT_ITE_INVALID 0x10310 0 1 UEE An INT command has tried to raise an interrupt with an EventID that is not supported by the corresponding MAPD command.
CLEAR_DEVICE_OOR 0x10501 0 1 CEE

A CLEAR has attempted to use a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

CLEAR_UNMAPPED_DEVICE 0x10504 0 1 CEE A CLEAR has tried to drop an interrupt from a device that is not mapped.
CLEAR_ID_OOR 0x10505 0 1 CEE A CLEAR has tried to drop an interrupt from an EventID that is not supported by the corresponding MAPD command.
CLEAR_UNMAPPED_INTERRUPT 0x10507 0 1 CEE A CLEAR has attempted to drop an interrupt that is not mapped.
CLEAR_ITE_INVALID 0x10510 0 1 CEE A CLEAR has tried to drop an interrupt from an EventID that is not supported by the corresponding MAPD command.
CLEAR_PHYSICALID_OOR 0x10526 1 1 CEE A CLEAR has tried to drop an interrupt, which has a physical ID that is not supported by the target.
CLEAR_TGT_OOR 0x10520 1 1 CEE A CLEAR has been sent to an illegal target.
CLEAR_LPI_OFF 0x10523 1 1 CEE A CLEAR has been sent to a target that does not have LPIs enabled.
CLEAR_CHIP_OFFLINE_OOR 0x10522 1 1 CEE A CLEAR has been sent to a target on a chip that is offline.
OPR_ DEVICE_OOR 0x10A01 1 - -

Software has tried an operation through GITS_OPR using a device that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

OPR_ UNMAPPED_COLLECTION 0x10A03 1 - -

Software has tried an operation through GITS_OPR using a collection that is outside the range that the ITS supports.

See GITS_BASER0c, and for information about the supported range, see GITS_TYPER.

OPR_ ID_OOR 0x10A05 1 - -

Software has tried to lock an interrupt using an EventID that is larger than the specified device supports.

The GITS_OPSR reports a fail.

OPR_ UNMAPPED_DEVICE 0x10A04 1 - -

Software has tried to lock an interrupt from a device that is not mapped through GITS_OPR.

The GITS_OPR reports a fail.

OPR_ UNMAPPED_INTERRUPT 0x10A07 1 - -

Software has tried to lock an interrupt that is not mapped through GITS_OPR.

The GITS_OPSR reports a fail.

OPR_ SET_LOCKED 0x10A10 1 - -

Software has tried to lock an interrupt into the cache but the set already contains a locked interrupt.

The GITS_OPSR reports a fail.

INVALID_ML_DEV_TABLE_ENTRY 0x10B04 1 1 CEE

Software is using a two-level Device table and the first-level table entry has not completed.

Software must allocate and clear a new second-level table, update the first-level entry, and repeat the command.

ACE_LITE_ACCESS_FAILURE 0x10B01 1 - -

An access that the ITS issues, receives an SLVERR or DECODE error.

The address is given in GICT_ERR<n>MISC1. This error can occur from multiple sources.

Software must determine whether the Command queue is stalled, by checking GITS_OPR. If the Command queue has stalled, the command might not have occurred.
ACE_LITE_TRANS_FAILURE 0x10B03 1 - AEE

An unknown source in the system has written to the slave port with an access that is not a legal GITS_TRANSLATER access.

The full address of the access is given in GICT_ERR<n>MISC1.

If the address matches GITS_TRANSLATER, either the size, length, strobes, or access type is wrong.

Note:

Read accesses are not tracked.
ACE_LITE_ADDR_OOR 0x10B05 1 - - ITS programming has tried to create an access to the address specified in GICT_ERR<n>MISC1 that is larger than the address space supported.
INVALID_COMMAND 0x10F00 1 - CEE

An Invalid command has been detected in the Command queue.

Software must correct this and then resume.

Clearing error records

After reading a GICT_ERR<n>STATUS register, software must clear the valid register bits so that any new errors are recorded.

During this period, a new error might overwrite the syndrome for the error that was read previously. If the register is read or written, the previous error is lost.

To prevent this, most bits use a modified version of write-1-to-clear:

  • Writes to the ERR<n>STATUS.UE (uncorrectable error records) or ERR<n>STATUS.CE (correctable error records) bits are ignored if ERR<n>STATUS.OF is set and is not being cleared.
  • Writes to other fields in the ERR<n>STATUS register are ignored if either ERR<n>STATUS.UE or ERR<n>STATUS.CE are set and are not being cleared.

Similarly, ERR<n>MISC<x> cannot be written, except the counter fields, if the corresponding ERR<n>STATUS.MV bit is set, and ERR<n>ADDR cannot be written if ERR<n>STATUS.AV is set.

Recommended recovery sequences are described for each error record in Software error record 0 to ITS command and translation error records 13+.

a Always packed from 0 (lowest = 0).
b Pending bits[13:12] indicate if there were pending interrupts in the cache at the time of the corruption.
c The Arm® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 describes this register.
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