|Home > Programmer's model > GICP register summary > Overflow Status Clear Register 0, GICP_OVSCLR0|
This register provides the clear mechanism for the counter overflow status bits and provides read access to the counter overflow status bit values. The GIC-600 supports five counters, n = 0-4.
The GICP_OVSCLR0 characteristics are:
|Usage constraints||There are no usage constraints.|
|Configurations||Available in all GIC-600 configurations.|
|Attributes||See 4.9 GICP register summary.|
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 4-67 GICP_OVSCLR0 bit assignments
Overflow status. The OVS[n] bit is the overflow clear for counter n. This field resets to zero.
Writing 1 to a bit location clears the overflow status for the associated counter.
Writing 0 to a bit location has no effect. To set a counter overflow status, use the GICP_OVSSET0 register.
Reads return the state of the overflow status bits.
Overflow of counter n, that is a transition past the maximum unsigned value of the counter that causes the value to wrap and become zero, and sets the corresponding OVS bit. In addition, this event can trigger the PMU interrupt and cause a capture of the PMU counter values, see 4.9.2 Event Type Configuration Registers, GICP_EVTYPERn.