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You can assign a recorded correctable ECC error to the fault_handling interrupt by setting GICT_ERR<n>CTLR.CFI.
All correctable ECC errors have error counters, therefore, the interrupt only fires when the counter in the associated GICT_ERR<c>MISC0 register overflows. You can preset the counter to any value by writing to GICT_ERR<c>MISC0.Count. For example, to fire an interrupt on any correctable error, write
0xFF, or to fire an interrupt on every second correctable error, write
You can assign a recorded uncorrectable ECC error either to the fault-handling interrupt, fault_int, by setting GICT_ERR<n>CTLR.FI, or to the error recovery interrupt, err_int, by setting GICT_ERR<n>CTLR.UI. The interrupt fires on every uncorrectable interrupt occurrence irrespective of the counter value.
You can route interrupts fault_int and err_int out as interrupt wires for situations where error recovery is handled by a core that does not receive interrupts directly from the GIC, such as a central system control processor. Alternatively, you can drive each interrupt internally by programming the associated GICT_ERRIRQCR<n> register.
Each GICT_ERRIRQCR<n> register contains an ID field that must be programmed to 0 if internal routing is not required, or if internal routing is required, to a legally supported SPI ID. If the programmed ID value is less than 32, out of range, or for multichip configurations, not owned on chip, the register updates to 0 and no internal delivery occurs.
Arm recommends that if the err_int and fault_int are internally routed, the target interrupts must not have SPI Collator wires, or if they are present, are tied off. This prevents software checking for the same ID at multiple destinations.
The err_int and fault_int do not have direct test enable registers. You can test connectivity using error record 0 and triggering an error, such as an illegal AXI access to a non-existent register.