11.8.61 Integration Test Registers

To access the Integration Test Registers registers, you must first set bit[0] of the Integration Mode Control Register to 0b1.

  • You can use the write-only Integration Test Registers to set the outputs of some of the ETM signals. The following table shows the signals that can be controlled in this way.
  • You can use the read-only Integration Test Registers to read the state of some of the ETM input signals. The Input signals that the Integration Test Registers can read table shows the signals that can be read in this way.

See the ARM® Embedded Trace Macrocell Architecture Specification ETMv4 for details of TRCITCTRL.

Output signals that the Integration Test Registers can control

Details of the output signals that the Integration Test Registers can control.

Table 11-84 Output signals that the Integration Test Registers can control

Signal Register Bits Register description
AFREADYMDx TRCITDATBOUTR [1] See Integration Data ATB Out Register
AFREADYMIx TRCITIATBOUTR [1] See Integration Instruction ATB Out Register
ATBYTESMDx[2:0] TRCITDATBOUTR [10:8] See Integration Data ATB Out Register
ATBYTESMIx[1:0] TRCITIATBOUTR [9:8] See Integration Instruction ATB Out Register
ATDATAMDx[63, 55, 47, 39, 31, 23, 15, 7, 0] TRCITDDATAR [8:0] See Integration Data ATB Data Register
ATDATAMIx[31, 23, 15, 7, 0] TRCITIDATAR [4:0] See Integration Instruction ATB Data Register
ATIDMDx[6:0] TRCITATBIDR [6:0] See Integration ATB Identification Register
ATIDMIx[6:0] TRCITATBIDR [6:0] See Integration ATB Identification Register
ATVALIDMDx TRCITDATBOUTR [0] See Integration Data ATB Out Register
ATVALIDMIx TRCITIATBOUTR [0] See Integration Instruction ATB Out Register
ETMACTIVEx TRCITMISCOUTR [5] See Integration Miscellaneous Outputs Register
ETMEXTOUT[3:0] TRCITMISCOUTR [11:8] See Integration Miscellaneous Outputs Register

Input signals that the Integration Test Registers can read

Table 11-85 Input signals that the Integration Test Registers can read

Signal Register Bits Register description
AFVALIDMDx TRCITDATBINR [1] See Integration Data ATB In Register
ATREADYMDx TRCITDATBINR [0] See Integration Data ATB In Register
AFVALIDMIx TRCITIATBINR [1] See Integration Instruction ATB In Register
ATREADYMIx TRCITIATBINR [0] See Integration Instruction ATB In Register
CPUACTIVE TRCITMISCINR [4] See Integration Miscellaneous Inputs Register
DBGACK TRCITMISCINR [5] See Integration Miscellaneous Inputs Register
ETMEVENT[3:0] TRCITMISCINR [3:0] See Integration Miscellaneous Inputs Register

Using the Integration Test Registers

You must not attempt to write to an Integration Test Register unless you have set bit[0] of TRCITCTRL to 0b1.

When bit[0] of TRCITCTRL is set to 0b1:

  • Values written to the write-only integration test registers map onto the specified outputs of the macrocell. For example, writing 0x3 TRCITMISCOUTR[11:8] causes ETMEXTOUT[3:0] to take the value 0x3.
  • Values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read TRCITMISCINR[3:0] you obtain the value of ETMEXTIN[3:0].

When bit[0] of TRCITCTRL is set to 0b0:

  • Reading an Integration Test Register returns an unpredictable value.
  • The effect of attempting to write to an Integration Test Register, other than the read-only Integration Test Registers, is unpredictable.

The ARM® Cortex®‑R8 MPCore Processor Integration Manual gives a full description of the use of the Integration Test Registers to check integration.

Integration Miscellaneous Outputs Register

The TRCITMISCOUTR sets the state of the output pins for ETMEXTOUT[3:0] and ETMACTIVEx.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 951

Base offset 0xEDC

Name: TRCITMISCOUTR

Type: RW

Reset: -

The following figure shows the TRCITMISCOUTR bit assignments.

Figure 11-72 TRCITMISCOUTR bit assignments
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The following table shows the TRCITMISCOUTR bit assignments.

Table 11-86 TRCITMISCOUTR bit assignments

Bits Name Function
[31:12] - Reserved. Write as zero.
[11:8] EXTOUT Drives the ETMEXTOUT[3:0] output pinsa.
[7:6] - Reserved. Write as zero.
[5] ACTIVE Drives the ETMACTIVEx output pina.
[4:0] - Reserved. Write as zero.

Integration Miscellaneous Inputs Register

TBD

The TRCITMISCINR reads the state of the input pins for the DBGACK, CPUACTIVE, and ETMEVENT[3:0] signals.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The values of the register bits depend on the signals on the input pins when the register is read.
Configurations
Available in all configurations.
Attributes

Register number: 952

Base offset 0xEE0

Name: TRCITMISCINR

Type: RO

Reset: -

The following figure shows the TRCITMISCINR bit assignments.

Figure 11-73 TRCITMISCINR bit assignments
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The following table shows the TRCITMISCINR bit assignments.

Table 11-87 TRCITMISCINR bit assignments

Bits Name Function
[31:6] - Reserved. Read undefined.
[5] DBGACK Returns the value of the DBGACK input pinb.
[4] CPUACTIVE Returns the value of the CPUACTIVE input pinb.
[3:0] EXTIN Returns the value of the ETMEVENT[3:0] input pinsb.

Integration ATB Identification Register

The TRCITATBIDR sets the state for the ATIDMDx[6:0] and ATIDMIx[6:0] output pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 953

Base offset 0xEE4

Name: TRCITATBIDR

Type: RW

Reset: -

The following figure shows the TRCITATBIDR bit assignments.

Figure 11-74 TRCITATBIDR bit assignments
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The following table shows the TRCITATBIDR bit assignments.

Table 11-88 TRCITATBIDR bit assignments

Bits Name Function
[31:7] - Reserved. Read undefined.
[6:0] ID Drives the ATIDMDx[6:0] and ATIDMIx[6:0] output pinsc.

Integration Data ATB Data Register

The TRCITDDATAR sets the state of the ATDATAMDx[63, 55, 47, 39, 31, 23, 15, 7, 0] output pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 954

Base offset 0xEE8

Name: TRCIRDDATAR

Type: RW

Reset: -

The following figure shows the TRCITDDATAR bit assignments.

Figure 11-75 TRCITDDATAR bit assignments
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The following table shows the TRCITDDATAR bit assignments.

Table 11-89 TRCITDDATAR bit assignments

Bits Name Function
[31:9] - Reserved. Write as zero.
[8:0] ATDATAMD Drives the ATDATAMDx[63, 55, 47, 39, 31, 23, 15, 7, 0] output pinsd.

Integration Instruction ATB Data Register

The TRCITIDATAR sets the state of the ATDATAMIx[31, 23, 15, 7, 0] output pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 955

Base offset 0xEEC

Name: TRCITIDATAR

Type: RW

Reset: -

The following figure shows the TRCITIDATAR bit assignments.

Figure 11-76 TRCITIDATAR bit assignments
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The following table shows the TRCITIDATAR bit assignments.

Table 11-90 TRCITIDATAR bit assignments

Bits Name Function
[31:5] - Reserved. Write as zero.
[4:0] ATDATAMI Drives the ATDATAMIx[31, 23, 15, 7, 0] output pinse.

Integration Data ATB In Register

The TRCITDATBINR reads the state of the AFVALIDMDx input pin.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The values of the register bits depend on the signals on the input pins when the register is read.
Configurations
Available in all configurations.
Attributes

Register number: 956

Base offset 0xEF0

Name: TRCITDATBINR

Type: RO

Reset: -

The following figure shows the TRCITDATBINR bit assignments.

Figure 11-77 TRCITDATBINR bit assignments
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The following table shows the TRCITDATBINR bit assignments.

Table 11-91 TRCITDATBINR bit assignments

Bits Name Function
[31:2] - Reserved. Read undefined.
[1] AFVALIDM Returns the value of the AFVALIDMDx input pinf.
[0] ATREADYM Returns the value of the ATREADYMDx input pinf.

Integration Instruction ATB In Register

The TRCITIATBINR reads the state of the AFVALIDMIx and ATREADYMIx input pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The values of the register bits depend on the signals on the input pins when the register is read.
Configurations
Available in all configurations.
Attributes

Register number: 957

Base offset 0xEF4

Name: TRCITIATBINR

Type: RO

Reset: -

The following figure shows the TRCITIATBINR bit assignments.

Figure 11-78 TRCITIATBINR bit assignments
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The following table shows the TRCITIATBINR bit assignments.

Table 11-92 TRCITIATBINR bit assignments

Bits Name Function
[31:2] - Reserved. Read undefined.
[1] AFVALIDM Returns the value of the AFVALIDMIx input pin.
[0] ATREADYM Returns the value of the ATREADYMIx input ping.

Integration Data ATB Out Register

The TRCITDATBOUTR sets the state of the ATBYTESMDx[2:0], AFREADYMDx, and ATVALIDMDx output pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 958

Base offset 0xEF8

Name: TRCITDATBOUTR

Type: RW

Reset: -

The following figure shows the TRCITDATBOUTR bit assignments.

Figure 11-79 TRCITDATBOUTR bit assignments
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The following table shows the TRCITDATBOUTR bit assignments.

Table 11-93 TRCITDATBOUTR bit assignments

Bits Name Function
[31:11] - Reserved. Read undefined.
[10:8] BYTES Drives the ATBYTESMDx[2:0] output pins.
[7:2] - Reserved. Read undefined.
[1] AFREADY Drives the AFREADYMDx output pinh.
[0] ATVALID Drives the ATVALIDMDx output pinh.

Integration Instruction ATB Out Register

The TRCITIATBOUTR sets the state of the ATBYTESMIx[1:0], AFREADYMIx, and ATVALIDMIx output pins.

Usage constraints
  • Available when bit[0] of TRCITCTRL is set to 0b1.
  • The value of the register sets the signals on the output pins when the register is written.
Configurations
Available in all configurations.
Attributes

Register number: 959

Base offset 0xEFC

Name: TRCITIATBOUTR

Type: RW

Reset: -

The following figure shows the TRCITIATBOUTR bit assignments.

Figure 11-80 TRCITIATBOUTR bit assignments
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The following table shows the TRCITIATBOUTR bit assignments.

Table 11-94 TRCITIATBOUTR bit assignments

Bits Name Function
[31:10] - Reserved. Read undefined.
[9:8] BYTES Drives the ATBYTESMIx[1:0] output pins.
[7:2] - Reserved. Read undefined.
[1] AFREADY Drives the AFREADYMIx output pini.
[0] ATVALID Drives the ATVALIDMIx output pini.
a When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. The TRCITMISCOUTR bit values correspond to the physical state of the output pins.
b When an input pin is LOW, the corresponding register bit is 0b0. When an input pin is HIGH, the corresponding register bit is 0b1. The TRCITMISCINR bit values always correspond to the physical state of the input pins.
c Bits[6:1] drive both ATIDMDx[6:1] and ATIDMIx[6:1]. Bit[0] drives ATIDMIx[0]. When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. ATIDMDx[0] is always driven HIGH. The TRCITATBIDR bit values correspond to the physical state of the output pins.
d When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. The TRCITDDATAR bit values correspond to the physical state of the output pins.
e When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. The TRCITIDATAR bit values correspond to the physical state of the output pins.
f When an input pin is LOW, the corresponding register bit is 0b0. When an input pin is HIGH, the corresponding register bit is 0b1. The TRCITDATBINR bit values always correspond to the physical state of the input pins.
g When an input pin is LOW, the corresponding register bit is 0b0. When an input pin is HIGH, the corresponding register bit is 0b1. The TRCITIATBINR bit values always correspond to the physical state of the input pins.
h When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. The TRCITDATBOUTR bit values always correspond to the physical state of the output pins.
i When a bit is set to 0b0, the corresponding output pin is LOW. When a bit is set to 0b1, the corresponding output pin is HIGH. The TRCITIATBOUTR bit values always correspond to the physical state of the output pins.
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