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The MPU can generate background faults, permission faults, and alignment faults. When a fault occurs, the memory access or instruction fetch is synchronously aborted, and a Prefetch Abort or Data Abort exception is taken as appropriate. No memory accesses are performed on the AXI3 bus master interface.
A background fault is generated when the MPU is enabled and a memory access is made to an address that is not within an enabled subregion of an MPU region. A background fault does not occur if the background region is enabled and the access is Privileged.
A permission fault is generated when a memory access does not meet the requirements of the permissions defined for the memory region that it accesses.
An alignment fault is generated if a data access is performed to an address that is not aligned for the size of the access, and strict alignment is required for the access. Several instructions that access memory, for example,
STC, require strict alignment.
See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition for more information. In addition, strict alignment can be required for all data accesses by setting the A-bit in the System Control Register.