9.3.12 SCU Debug tag RAM access

You can access a specific faulty location in a tag RAM or inject fake errors to check the ECC mechanism in the SCU.

Three SCU registers are provided:

  • SCU Debug Tag RAM Operation Register to select the type of operation and the selected tag RAM.
  • SCU Debug Tag RAM Data Value Register to select a specific tag value.
  • SCU Debug Tag RAM ECC Chunk Register to select the ECC chunk associated with the tag value.

To read a given SCU tag RAM location:

  1. Write the SCU Debug Tag RAM Operation Register.
  2. Read the SCU Debug Tag RAM Data Value Register or the SCU Debug Tag RAM ECC Chunk Register.

To write a given SCU tag RAM location:

  1. Write the SCU Debug Tag RAM Data Value Register or the SCU Debug Tag RAM ECC Chunk Register.
  2. Write the SCU Debug Tag RAM Operation Register.

SCU Debug Tag RAM Operation Register

The SCU Debug Tag RAM Operation Register gives the address and action for SCU tag RAM direct access.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x70

Reset value: -

The following figure shows the SCU Debug Tag RAM Operation Register bit assignments.

Figure 9-13 SCU Debug Tag RAM Operation Register bit assignments
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The following table shows the SCU Debug Tag RAM Operation Register bit assignments.

Table 9-14 SCU Debug Tag RAM Operation Register bit assignments

Bits Name Function
[31:30] SCU tag RAM way target Indicates the number of the RAM way.
[29:26] - Reserved. SBZ.
[25:24] SCU tag RAM core target

Indicates the core target:

0b00Core 0.
0b01Core 1.
0b10Core 2.
0b11Core 3.
[23:14] - Reserved. SBZ.
[13:5] SCU tag RAM set target Index to read or write the SCU tag RAM.
[4:1] - Reserved. SBZ.
[0] Read or write operation

Specifies whether it is a read or write operation:

0b0Read.
0b1Write.

SCU Debug Tag RAM Data Value Register

The SCU Debug Tag RAM Data Value Register gives the data value for SCU tag RAM direct access.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x74

Reset value: -

The following figure shows the SCU Debug Tag RAM Data Value Register bit assignments.

Figure 9-14 SCU Debug Tag RAM Data Value Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the SCU Debug Tag RAM Data Value Register bit assignments.

Table 9-15 SCU Debug Tag RAM Data Value Register bit assignments

Bits Name Function
[31:23] - Reserved. SBZ.
[22] Valid Valid bit.
[21:17] Value

Tag value:

[21]
4KB.
[21:20]
8KB.
[21:19]
16KB.
[21:18]
32KB.
[21:17]
64KB.

Unused bits are Reserved.

[16:0] - Reserved. SBZ.

SCU Debug Tag RAM ECC Chunk Register

The SCU Debug Tag RAM ECC Chunk Register shows the ECC chunk value.

Usage constraints
There are no usage constraints.
Configurations
Available only in configurations where ECC is implemented.
Attributes

Offset from PERIPHBASE[31:13]: 0x78

Reset value: -

The following figure shows the SCU Debug Tag RAM ECC Chunk Register bit assignments.

Figure 9-15 SCU Debug Tag RAM ECC Chunk Register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the SCU Debug Tag RAM ECC Chunk Register bit assignments.

Table 9-16 SCU Debug Tag RAM ECC Chunk Register bit assignments

Bits Name Function
[31:7] - Reserved. SBZ.
[6:0] Chunk ECC chunk value.
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