10.4.2 Debug registers

Technical reference information for the debug registers.

Register interfaces

The Cortex®‑R8 processor implements Baseline CP14, Extended CP14, and memory-mapped interfaces.

You can access the debug registers as follows:

  • Through the cp14 interface. The debug registers are mapped to coprocessor instructions.
  • Through the APB using the relevant offset.

Debug register mapping table

Mapping for the debug registers.

All other registers are described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.

Table 10-8 Debug register mapping

Register number APB offset APB access CP14 address CP14 access Register name Description
0 0x000 RO 0, c0, c0, 0 RO DBGDIDRa -b
128 No access No access 0, c1, c0, 0 RO DBGDRARa -
256 No access No access 0, c2, c0, 0 RO DBGDSARa -
1 No access No access 0, c0, c1, 0 RO DBGDSCRintab -
5 No access No access 0, c0, c5, 0 RO DBGDTRRXinta -
No access No access WO DBGDTRTXinta -
6 0x018 RW 0, c0, c6, 0 RW DBGWFAR Use of DBGWFAR is deprecated in the ARMv7 architecture, because watchpoints are synchronous
7 0x01C RW 0, c0, c7, 0 RW DBGVCR -
8 - - - - Reserved -
9 No access No access 0, c0, c9, 0 RAZ/WI DBGECR Not implemented
10 No access No access 0, c0, c10, 0 RAZ/WI DBGDSCCR Not implemented
11 No access No access 0, c0, c11, 0 RAZ/WI DBGDSMCR Not implemented
12-31 - - - - Reserved -
32 0x080 RW 0, c0, c0, 2 RW DBGDTRRXext -
33 0x084 WO 0, c0, c1, 2 WO DBGITR -
33 0x084 RO 0, c0, c1, 2 RO DBGPCSR -
34 0x088 RW 0, c0, c2, 2 RW DBGDSCRext -
35 0x08C RW 0, c0, c3, 2 RW DBGDTRTXext -
36 0x090 WO 0, c0, c4, 2 WO DBGDRCR -
37-63 - - - - Reserved -
64-69 0x100-0x114 RW 0, c0, c0-c5, 4 RW DBGBVRn Breakpoint Value Registers
70-79 - - - - Reserved -
80-85 0x140-0x154 RW 0, c0, c0-c5, 5 RW DBGBCRn Breakpoint Control Registers
86-95 - - - - Reserved -
96-99 0x180-0x18C RW 0, c0, c0-c3, 6 RW DBGWVRn Watchpoint Value Registers
100-111 - - - - Reserved -
112-115 0x1C0-0x1CC RW 0, c0, c0-c3, 7 RW DBGWCRn Watchpoint Control Registers
116-191 - - - - Reserved -
192 0x300 RAZ/WI 0, c1, c0, 4 RAZ/WI DBGOSLAR Not implemented
193 0x304 RAZ/WI 0, c1, c1, 4 RAZ/WI DBGOSLSR Not implemented
194 0x308 RAZ/WI 0, c1, c2, 4 RAZ/WI DBGOSSRR Not implemented
195 - - - - Reserved -
196 0x310 RW 0, c1, c4, 4 RW DBGPRCR -
197 0x314 RO 0, c1, c5, 4 RO DBGPRSR -
198-511 - - - - Reserved -
512-575 0x800-0x8FC - - - - PMU registersc
576-831 - - - - Reserved -
832-895 0xD00-0xDFC - - - - Processor ID Registers
896-927 -   -   Reserved -
928-959 0xE80-0xEFC RAZ/WI No access No access - -
960 0xF00 RAZ/WI 0, c7, c0, 4 RAZ/WI DBGITCTRL Integration Mode Control Register
961-999 0xF04-0xF9C - - - - -
1000 0xFA0 RW 0, c7, c8, 6 RW DBGCLAIMSET Claim Tag Set Register
1001 0xFA4 RW 0, c7, c9, 6 RW DBGCLAIMCLR Claim Tag Clear Register
1002-1003 - - - - Reserved -
1004 0xFB0 WO No access No access DBGLAR Lock Access Register
1005 0xFB4 RO No access No access DBGLSR Lock Status Register
1006 0xFB8 RO 0, c7, c14, 6 RO DBGAUTHSTATUS Authentication Status Register
1007-1008 - - - - Reserved -
1009 0xFC4 RO No access No access DBGDEVID1 -
1010 0xFC8 RO No access No access DBGDEVID0 -
1011 0xFCC RO No access No access DBGDEVTYPE Device Type Register
1012-1016 0xFD0-0xFEC RO No access No access PERIPHERALID CoreSight Identification Registers
1017-1019 - - - - Reserved -
1020-1023 0xFF0-0xFFC RO No access No access COMPONENTID CoreSight Identification Registers

Debug register descriptions

Register features that are specific to the Cortex®‑R8 processor.

See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition for information about other register features not described in this section.

Debug ID Register, DBGDIDR

The DBGDIDR specifies the version of the Debug architecture that is implemented, and some features of the debug implementation.

Usage constraints

There are no usage constraints.

Accessible when the processor is powered down.

For more information about the debug implementation, see Debug Device ID Register 1 and Debug Device ID Register 0.

Configurations
Available in all configurations.
Attributes
See the register summary in Debug register mapping table.

The following figureshows the DBGDIDR bit assignments.

Figure 10-1 DBGDIDR bit assignments
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The following table shows the DBGDIDR bit assignments.

Table 10-9 DBGDIDR bit assignments

Bits Name Function
[31:28] WRPs Indicates the number of Watchpoint Register Pairs (WRPs) implemented:
0x3The processor implements 4 WRPs.
[27:24] BRPs Indicates the number of Breakpoint Register Pairs (BRPs) implemented:
0x5The processor implements 6 BRPs.
[23:20] CTX_CMPs Indicates the number of BRPs that can be used for Context matching:
0x1The processor implements 2 breakpoints with Context matching.
[19:16] Version Indicates the Debug architecture version:
0x3The processor implements ARMv7 Debug architecture.
[15] DEVID_imp Indicates if the Debug Device ID Register (DBGDEVID) is implemented:
1DBGDEVID is implemented.
[14] nSUHD_imp Indicates if the Secure User Halting Debug is implemented:
0Secure User halting debug is implemented.
[13] PCSR_imp Indicates if the Program Counter Sampling Register (DBGPCSR) implemented as register 33:
1DBGPCSR is implemented as register 33.
[12] SE_imp Security Extensions implemented bit:
0Security Extensions are not implemented.
[11:8] - Reserved.
[7:4] Variant Indicates the variant number of the processor. This number is incremented on functional changes. The value matches bits [23:20] of the CP15 Main ID Register. For more information, see 4.3.1 Main ID Register.
[3:0] Revision Indicates the revision number of the processor. This number is incremented on bug fixes. The value matches bits [3:0] of the CP15 Main ID Register. For more information, see 4.3.1 Main ID Register.
Debug Status and Control Register, DBGDSCR

Bit exceptions for DBGDSCR.

DBGDSCR behaves as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition, except for the following bits:

PipeAdv, bit[25]
This bit is set each time a branch is resolved in the core.
HALTED, bit[0]
This bit is the only bit of the register that is not reset on debug logic reset. It is reset to 0b0 on a core logic reset. Its behavior is as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
Debug Run Control Register, DBGDRCR

Bit exceptions for DBGDRCR.

DBGDRCR behaves as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition, except for the following bits:

Cancel BIU Requests, bit[4]
Not implemented, RAZ/WI.
Bits[3:0]
Implemented as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
Device Powerdown and Reset Control Register, DBGPRCR

Bit exceptions for DBGPRCR.

DBGPRCR behaves as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition, except for the following bits:

Bits[2:1]
Not implemented, RAZ/WI.
DBGnoPWRDWN, bit[0]
Implemented as described in the ARM® Architecture Reference ManualARMv7-A and ARMv7‑R edition (RW).
Device Powerdown and Reset Status Register, DBGPRSR

Bit exceptions for DBGPRSR.

DBGPRSR behaves as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition, except for the following bits:

Sticky Reset Status, bit[3]
Implemented as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
Reset Status, bit[2]
Implemented as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
Sticky Powerdown Status, bit[1]
Not implemented, RAZ/WI.
Power-up Status, bit[0]
Implemented, RAO.
Debug Device ID Register 1

The DBGDEVID1 adds to the information given by the DBGDIDR, by describing other features of the debug implementation.

Usage constraints

There are no usage constraints.

Accessible when the processor is powered down.

Attributes
See the register summary in Debug register mapping table.

The following figure shows the DBGDEVID1 bit assignments.

Figure 10-2 DBGDEVID1 bit assignments
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The following table shows the DBGDEVID1 bit assignments.

Table 10-10 DBGDEVID1 bit assignments

Bits Name Function
[31:4] - Reserved.
[3:0] PCSROffset Defines the offset applied to DBGPCSR samples:
0b0001DBGPCSR samples have no offset applied.
Debug Device ID Register 0

The DBGDEVID0 extends the DBGDIDR by describing other features of the debug implementation.

Usage constraints

Use in conjunction with DBGDIDR to find the features of the debug implementation. See the Debug ID Register for the DBGDIDR bit assignments.

Accessible when the processor is powered down.

Configurations
Available in all configurations.
Attributes
See the register summary in Debug register mapping table.

Figure 9-20 shows the DBGDEVID0 bit assignments.

Figure 10-3 DBGDEVID0 bit assignments
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Table 9-19 shows the DBGDEVID0 bit assignments.

Table 10-11 DBGDEVID0 bit assignments

Bits Name Function
[31:28] CIDMask This field indicates the level of support for the Context ID matching breakpoint masking capability.
0b0000Context ID masking not implemented.
[27:24] AuxRegs Specifies support for the Debug External Auxiliary Control Register.
0b0000The processor does not support the Debug External Auxiliary Control Register.
[23:20] DoubleLock Specifies support for the Debug OS Double Lock Register:
0b0000The Debug OS Double-lock Register is not supported.
[19:16] VirExtns Specifies the implementation of the Virtualization Extensions to the Debug architecture:
0b0000Virtualization Extensions to the Debug architecture are not implemented.
[15:12] VectorCatch Defines the form of the vector catch event implemented:
0b0000The processor implements address matching form of vector catch.
[11:8] BPAddrMask Indicates the level of support for the Immediate Virtual Address (IVA) matching breakpoint masking capability:
0b1111Breakpoint address masking not implemented. DBGBCRn[28:24] are UNK/SBZP.
[7:4] WPAddrMask Indicates the level of support for the DVA matching watchpoint masking capability:
0b0001Watchpoint address mask implemented.
[3:0] PCSample Indicates the level of support for Program Counter sampling using debug registers 40 and 41:
0b0000Program Counter Sampling Register (DBGPCSR) is not implemented as register 40, and Context ID Sampling Register (DBGCIDSR) is not implemented.
Breakpoint and Watchpoint Registers, DBGBVRn, DBGBCRn, DBGWVRn, and DBGWCRn

Breakpoint and Watchpoint Registers features that are specific to the Cortex®‑R8 processor.

The Breakpoint and Watchpoint Registers behave as described in the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition, except for the following:

  • Only BRP4 and BRP5 support context ID comparison.
  • BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are SBZP on writes and RAZ on reads because these registers do not support context ID comparisons.
  • The context ID value for a BVR to match with is given by the contents of the CP15 Context ID Register.

Effects of resets on debug registers

nDBGRESET is the debug logic reset signal. This signal must be asserted during a power up reset sequence.

On a debug reset:

  • The debug state is unchanged. That is, DBGSCR.HALTED is unchanged.
  • The processor removes the pending halting debug events DBGDRCR.HaltReq.

Debug management registers

The management registers define the standardized set of registers that is implemented by all CoreSight™ components.

The following table shows the contents of the debug management registers for the Cortex‑R8 processor debug unit. On the Cortex‑R8 processor, the debug management registers are memory-mapped.

Table 10-12 Debug management registers

APB offset Register number Access Mnemonic Description
0xD00-0xDFC 832-895 RO - Processor ID Registers
0xE00-0xEF0 854-956 RAZ/WI - Not implemented
0xF00 960 RAZ/WI ITCTRL -
0xF04-0xF9C 961-999 RAZ/WI - Not implemented
0xFA0 1000 RW CLAIMSET -
0xFA4 1001 RW CLAIMCLR -
0xFA8-0xFBC 1002-1003 RAZ/WI - Not implemented
0xFB0 1004 WO LOCKACCESS -
0xFB4   RO LOCKSTATUS -
0xFB8   RO AUTHSTATUS -
0xFBC-0xFC4 1007-1009 RAZ/WI - Not implemented
0xFC8 1010 RO DEVID -
0xFCC 1011 RO DEVTYPE -
0xFD0-0xFFC 1012-1023 RO - CoreSight Identification Registers
Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the corresponding CP15 ID Code Register and Feature ID Register.

The Processor Identifier Registers table shows the APB offset value, register number, mnemonic, and description that are associated with each Processor ID Register.

CoreSight Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight™ components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the Cortex‑R8 processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

The following table shows the APB offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 10-13 Peripheral Identification Registers for core debug

APB offset Register number Value Description
0xFD0 1012 0x04 Peripheral Identification Register 4
0xFD4 1013 - Reserved
0xFD8 1014 - Reserved
0xFDC 1015 - Reserved
0xFE0 1016 0x18 Peripheral Identification Register 0
0xFE4 1017 0xBC Peripheral Identification Register 1
0xFE8 1018 0x0B Peripheral Identification Register 2
0xFEC 1019 0x00 Peripheral Identification Register 3

The following table shows the APB offset value, register number, and value that are associated with each Component Identification Register.

Table 10-14 Component Identification Registers

APB offset Register number Value Description
0xFF0 1020 0x0D Component Identification Register 0
0xFF4 1021 0x90 Component Identification Register 1
0xFF8 1022 0x05 Component Identification Register 2
0xFFC 1023 0xB1 Component Identification Register 3
a Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface.
b Accessible in user mode if bit[12] of the DBGSCR is clear. Also accessible in privileged modes.
c PMU registers are part of the CP15 interface. Reads from the extended CP14 interface return zero. See 4.2 Register summary. See also 10.1 Performance Monitoring Unit.
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