4.3.12 MPU memory region programming registers

The MPU memory region programming registers program the MPU regions.

There is one register that specifies which set of region registers is to be accessed. Each region has its own register to specify:

  • Region base address.
  • Region size and enable.
  • Region access control.

You can implement the processor with 12, 16, 20, or 24 regions.

Note:

  • When the MPU is enabled:

    • The MPU determines the access permissions for all accesses to memory, including the TCMs. Therefore, you must ensure that the memory regions in the MPU are programmed to cover the complete TCM address space with the appropriate access permissions. You must define at least one of the regions in the MPU.

    • An access to an undefined area of memory generates a background fault.
  • For the TCM space, the processor uses the access permissions but ignores the region attributes from MPU.

    CP15, c9 sets the location of the TCM base address.

MPU Region Base Address Registers

The DRBAR describe the base address of the region specified by the RGNR. The region base address must always align to the region size.

Usage constraints
The DRBAR are only accessible in privileged mode.
Configurations
Available in all configurations.
Attributes
See the c6 register summary, 4.2.4 c6 registers.

The following figure shows the DRBAR bit assignments.

Figure 4-11 DRBAR bit assignments
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The following table shows the DRBAR bit assignments.

Table 4-28 DRBAR bit assignments

Bits Name Function
[31:5] Base address Physical base address. Defines the base address of a region.
[4:0] - Reserved. SBZ.

To access the DRBAR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 0 ; Read MPU Region Base Address Register
MCR p15, 0, <Rd>, c6, c1, 0 ; Write MPU Region Base Address Register

MPU Region Size and Enable Registers

MPU Region Size and Enable Registers (DRSR) characteristics and bit assignments.

The DRSR:

  • Specify the size of the region specified by the RGNR.
  • Identify the address ranges that are used for a particular region.
  • Enable or disable the region, and its sub-regions, specified by the RGNR.

The following figure shows the DRSR bit assignments.

Figure 4-12 DRSR bit assignments
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The following table shows the DRSR bit assignments.

Table 4-29 DRSR bit assignments

Bits Name Function
[31:16] - Reserved. SBZ.
[15:8] Sub-region disable

Each bit position represents a sub-region, 0-7a.

Bit[8] corresponds to sub-region 0.

...

Bit[15] corresponds to sub-region 7.

The meaning of each bit is:

0b0Address range is part of this region.
0b1Address range is not part of this region.
[7:6] - Reserved. SBZ.
[5:1] Region size

Defines the region size:

0b00000-0b00110
unpredictable.
0b00111
256 bytes.
0b01000
512 bytes.
0b01001
1KB.
0b01010
2KB.
0b01011
4KB.
0b01100
8KB.
0b01101
16KB.
0b0111032KB.
0b0111164KB.
0b10000128KB.
0b10001256KB.
0b10010512KB.
0b100111MB.
0b101002MB.
0b101014MB.
0b101108MB.
0b1011116MB.
0b1100032MB.
0b1100164MB.
0b11010128MB.
0b11011256MB.
0b11100512MB.
0b111011GB.
0b111102GB.
0b111114GB.
[0] Enable

Enables or disables a memory region:

0b0Memory region disabled. Memory regions are disabled on reset.
0b1Memory region enabled. A memory region must be enabled before it is used.

To access the DRSR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 2 ; Read Data MPU Region Size and Enable Register
MCR p15, 0, <Rd>, c6, c1, 2 ; Write Data MPU Region Size and Enable Register

Writing a region size that is outside the range results in unpredictable behavior.

MPU Region Access Control Registers

The DRACR registers hold the region attributes and access permissions for the region specified by the RGNR.

Usage constraints
The DRACR are only accessible in privileged mode.
Configurations
Available in all configurations.
Attributes
See the c6 register summary, 4.2.4 c6 registers.

The following figure shows the DRACR bit assignments.

Figure 4-13 DRACR bit assignments
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The following table shows the DRACR bit assignments.

Table 4-30 DRACR bit assignments

Bits Name Function
[31:13] - Reserved. SBZ.
[12] XN

Execute never. Determines if a region of memory is executable:

0b0All instruction fetches enabled.
0b1No instruction fetches enabled.
[11] - Reserved. SBZ.
[10:8] AP Access permission. Defines the data access permissions. For more information on AP bit values, see MPU Region Access Control Registers.
[7:6] - Reserved. SBZ.
[5:3] TEX Type extension. Defines the type extension attribute. For more information on this region attribute, see 8.2.3 Region attributes.
[2] S

Share. Determines if the memory region is Shareable or Non-Shareable:

0b0Non-Shareable.
0b1Shareable.

This bit only applies to Normal, not Device or Strongly-Ordered memory.

[1] C C bit. For more information on this region attribute, see 8.2.3 Region attributes.
[0] B B bit. For more information on this region attribute, see 8.2.3 Region attributes.

The following table shows the AP bit values that determine the permissions for privileged and user data access.

Table 4-31 Access data permission bit encoding

AP bit values Privileged permissions User permissions Description
0b000 No access No access All accesses generate a permission fault
0b001 Read/write No access Privileged access only
0b010 Read/write Read-only Writes in user mode generate permission faults
0b011 Read/write Read/write Full access
0b100 UNP UNP Reserved
0b101 Read-only No access Privileged read-only
0b110 Read-only Read-only Privileged/user read-only
0b111 UNP UNP Reserved

To access the DRACR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c1, 4 ; Read Region Access Control Register
MCR p15, 0, <Rd>, c6, c1, 4 ; Write Region Access Control Register

To execute instructions in user and privileged modes:

  • The region must have read access as defined by the AP bits.
  • The XN bit must be set to 0b0.

MPU Memory Region Number Registers

The RGNR determine which register is accessed. There is one register for each implemented memory region.

Usage constraints
The RGNR are only accessible in privileged mode.
Configurations
Available in all configurations.
Attributes
See the c6 register summary, 4.2.4 c6 registers.

The following figure shows the RGNR bit assignments.

Figure 4-14 RGNR bit assignments
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The following table shows the RGNR bit assignments.

Table 4-32 RGNR bit assignments

Bits Name Function
[31:5] - Reserved. SBZ.
[4:0] Region Defines the group of registers to be accessed. Read the MPU Type Register to determine the number of supported regions, see 4.3.2 MPU Type Register.

To access the RGNR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c6, c2, 0 ; Read MPU Memory Region Number Register
MCR p15, 0, <Rd>, c6, c2, 0 ; Write MPU Memory Region Number Register

Writing this register with a value greater than or equal to the number of regions from the MPU Type Register is unpredictable. Associated register bank accesses are also unpredictable.

a Sub-region 0 covers the least significant addresses in the region, while sub-region 7 covers the most significant addresses in the region.
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