A.8.1 AXI master interface signals

Cortex®‑R8 processor AXI master interface signals.

The x at the end of the signal name represents either 0 for AXI master port 0 or 1 for the optional AXI master port 1.

AXI master interface clock enable signals

Details of the AXI master interface clock enable signals.

Table A-8 AXI master interface clock enable signals

Name Type Source/destination Description
INCLKENMx Input CLK

Clock bus enable for the AXI bus that enables the AXI interface to operate at either:

  • Integer ratios of the system clock.
  • Half integer ratios of the system clock.

Inputs are sampled on rising edges of CLK only when INCLKENMx is HIGH.

OUTCLKENMx Input

Clock bus enable for the AXI bus that enables the AXI interface to operate at either:

  • Integer ratios of the system clock.
  • Half integer ratios of the system clock.

Outputs are updated on rising edges of CLK only when OUTCLKENMx is HIGH.

AXI master interface read address signals

Details of the AXI master interface read address signals.

Table A-9 AXI master interface read address signals

Name Type Source/destination Description
ARADDRMx[31:0] Output AXI3 device Read address.
ARBURSTMx[1:0] Output

Read address burst type:

0b01INCR incrementing burst.
0b10WRAP wrapping burst.

All other values are reserved.

ARCACHEMx[3:0] Output Read address cache type giving additional information about cacheable characteristics.
ARIDMx[n]a Output Read address ID.
ARLENMx[3:0] Output AXI3 device

The number of data transfers that can occur within each burst. Cacheable traffic generates transactions with four data transfers. For a description of other traffic, see 12.1.1 Supported AXI3 transfers. Burst transactions from the ACP can be 1-16 transfers long.

0b00001 data transfer.
0b00012 data transfers.
0b00103 data transfers.
0b00114 data transfers.
0b01005 data transfers.
0b01016 data transfers.
0b01107 data transfers.
0b01118 data transfers.
0b10009 data transfers.
0b100110 data transfers.
0b101011 data transfers.
0b101112 data transfers.
0b110013 data transfers.
0b110114 data transfers.
0b111015 data transfers.
0b111116 data transfers.
ARLOCKMx[1:0] Output

Read address lock type:

0b00Normal access.
0b01Exclusive access.
0b10Locked access.
ARPROTMx[2:0] Output Read address protection type
ARREADYMx Input Read address ready
ARSIZEMx[1:0] Output

Read address burst size:

0b0008-bit transfer.
0b00116-bit transfer.
0b01032-bit transfer.
0b01164-bit transfer.
ARUSERMx[9:0] Output Read address transfer attributes. See 12.1.2 AXI3 USER bits.
ARVALIDMx Output Read address valid.

AXI master interface read data signals

Details of the AXI master interface read data signals.

Table A-10 AXI master interface read data signals

Name Type Source/destination Description
RDATAMx[63:0] Input AXI3 device Read data.
RDATAERRCODEMx[7:0] Input ECC bits on data bus, when BUS_ECC build parameter is set.
RIDMx[n] Input Read data ID.
RLASTMx Input Read data last indication.
RREADYMx Output Read data ready.
RRESPMx[1:0] Input Read data response.
RVALIDMx Input Read data valid.
SRENDMx[3:0] Input Speculative read information from optional L2 Cache Controller. See the ARM® CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference Manual for more information.
SRIDMx[n]b Input ID for speculative reads returned by L2 Cache Controller.

AXI master interface write address signals

Details of the AXI master interface write address signals.

Table A-11 AXI master interface write address signals

Name Type Source/destination Description
AWADDRMx[31:0] Output AXI3 device Write address.
AWBURSTMx[1:0] Output

Write address burst type:

0b01INCR incrementing burst.
0b10WRAP wrapping burst.

All other values are reserved.

AWCACHEMx[3:0] Output Write address cache type giving additional information about cacheable characteristics.
AWIDMx[n]c Output Write address channel ID.
AWLENMx[3:0] Output AXI3 device

The number of data transfers that can occur within each burst.

For a description of other processor-generated traffic, see 12.1.1 Supported AXI3 transfers. Burst transactions from the ACP can be 1-16 transfers long.

0b0001 data transfer.
0b0012 data transfers.
0b0103 data transfers.
0b0114 data transfers.
0b1005 data transfers.
0b1016 data transfers.
0b1107 data transfers.
0b1118 data transfers.
0b10009 data transfers.
0b100110 data transfers.
0b101011 data transfers.
0b101112 data transfers.
0b110013 data transfers.
0b110114 data transfers.
0b111015 data transfers.
0b111116 data transfers.
AWLOCKMx[1:0] Output

Write address lock type:

0b0Normal access.
0b1Exclusive access.
0b10Locked access.
AWPROTMx[2:0] Output Write address protection type.
AWREADYMx Input Write address ready.
AWSIZEMx[1:0] Output

Write address burst size:

0b008-bit transfer.
0b0116-bit transfer.
0b1032-bit transfer.
0b1164-bit transfer.
AWUSERMx[11:0] Output Write address transfer attributes. See 12.1.2 AXI3 USER bits.
AWVALIDMx Output Write address valid.

AXI master interface write data signals

Details of the AXI master interface write data signals.

Table A-12 AXI master interface write data signals

Name Type Source/destination Description
WDATAMx[63:0] Output AXI3 device Write data.
WIDMx[n]d Output Write data ID.
WLASTMx Output Write last indication.
WREADYMx Input Write ready.
WSTRBMx[7:0] Output Write byte-lane strobe.
WVALIDMx Output Write valid.
WUSERMx[2:0] Output Write data transfer attributes. See 12.1.2 AXI3 USER bits.

AXI master interface write response signals

Details of the AXI master interface write response signals.

Table A-13 AXI master interface write response signals

Name Type Source/destination Description
BIDMx[n]e Input L2C-310 or other system AXI3 devices Write response ID
BREADYMx Output Write response ready
BRESPMx[1:0] Input Write response
BVALIDMx Input Write response valid
a  You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
b You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
c You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
d You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
e You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
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