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Each Cortex®‑R8 processor core can be implemented with a dedicated fast peripheral port. This is a memory-mapped 32-bit AXI peripheral port that provides fast accesses to a dedicated peripheral.
The following table shows the AXI Fast Peripheral Port attributes.
Table 2-4 AXI Fast Peripheral Port attributes
|Write issuing capability||
|Read issuing capability||
|Combined issuing capability||12|
|Write interleave capability||1|
The FPP has optional ECC protection on data, and parity on control bits.
An FPP access to a core is determined by the FPP filtering start address and FPP filtering end address setup for that core and issued by the FPP dedicated to that core. Accesses that are outside of the address filtering range are directed either to the AXI master ports or to the AXI low-latency peripheral port.
The FPP, LLPP, and master port 1 each have a designated memory-mapped address filtering region. If an access overlaps the address filtering region of two ports, the access is routed to the port with the highest priority. The order of priority of each port is:
For example, if the access overlaps the FPP and LLPP regions, the FPP is accessed.
The start and end filtering addresses are configurable in the following SCU registers:
The granularity of the mapped memory is 1MB and is defined by the formula:
Memory_space (MB) = End to Start + 1.
This filtering rule is applied independently of the AXI request type and attributes.
When ACTLR.QoS is set for a core, all traffic using the corresponding FPP is treated as high priority. High priority traffic transfers can access either the AXI master port 1 with address filtering enabled, the FPP with address filtering enabled, the AXI low-latency peripheral port, or the data TCM. If the QoS bit is set for several cores, the SCU manages each type of high priority traffic by arbitration. ARM recommends that the QoS bit is set for one core only.