9.6.1 Global timer registers

Summary of the global timer registers. The offset is relative to PERIPH_BASE_ADDR + 0x0200. Use nPERIPHRESET to reset these registers.

Table 9-33 Global timer registers

Offset Type Reset value Description
0x00 RW 0x00000000 Global Timer Counter Registers
0x04 RW 0x00000000
0x08 RW 0x00000000 Global Timer Control Register
0x0C RW 0x00000000 Global Timer Interrupt Status Register
0x10 RW 0x00000000 Comparator Value Registers
0x14 RW 0x00000000
0x18 RW 0x00000000 Auto-increment Register

Global Timer Counter Registers

There are two timer counter registers. They are the lower 32-bit timer counter at offset 0x00 and the upper 32-bit timer counter at offset 0x04.

You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. Any other access is unpredictable.

To modify the register, proceed as follows:

  1. Clear the timer enable bit in the Global Timer Control Register.
  2. Write the lower 32-bit timer counter register.
  3. Write the upper 32-bit timer counter register.
  4. Set the timer enable bit.

To get the value from the Global Timer Counter register, proceed as follows:

  1. Read the upper 32-bit timer counter register.
  2. Read the lower 32-bit timer counter register.
  3. Read the upper 32-bit timer counter register again. If the value is different to the 32-bit upper value read previously, go back to step 2. Otherwise the 64-bit timer counter value is correct.

Global Timer Control Register

Global Timer Control Register bit assignments.

Figure 9-31 Global Timer Control Register bit assignments
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The following table shows the Global Timer Control Register bit assignments.

Table 9-34 Global Timer Control Register bit assignments

Bits Name Function
[31:16] - Reserved.
[15:8] Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register. See 9.5.1 Calculating timer intervals for the equation.
[7:4] - Reserved.
[3] Auto-incrementa

This bit is banked per Cortex‑R8 processor core:

0b0Single shot mode. Sets the event flag when the counter reaches the comparator value, . It is the responsibility of software to update the comparator value to get more events.
0b1Auto-increment mode. Each time the counter reaches the comparator value, the comparator register is incremented with the auto-increment register, so that more events can be set periodically without any software updates.
[2] IRQ enable

This bit is banked per Cortex‑R8 processor core.

If set, the interrupt ID 27 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.

[1] Comp enablea

This bit is banked per Cortex‑R8 processor core.

If set, it allows the comparison between the 64-bit Timer Counter and the related 64-bit Comparator Register.

[0] Timer enable

Timer enable:

0b0Timer is disabled and the counter does not increment. All registers can still be read and written.
0b1Timer is enabled and the counter increments normally.

Global Timer Interrupt Status Register

This is a banked register for all Cortex®‑R8 processor cores present.

The event flag is a sticky bit that is automatically set when the Counter Register reaches the Comparator Register value. If the timer interrupt is enabled, Interrupt ID 27 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1. The following figure shows the Global Timer Interrupt Status Register bit assignments.

Figure 9-32 Global Timer Interrupt Status Register bit assignments
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Comparator Value Registers

There are two 32-bit registers, the lower 32-bit comparator value register at offset 0x10 and the upper 32-bit comparator value register at offset 0x14.

You must access these registers with 32-bit accesses. You cannot use STRD/LDRD. There is a Comparator Value Register for each Cortex‑R8 processor core.

To ensure that updates to this register do not set the Interrupt Status Register, proceed as follows:

  1. Clear the Comp enable bit in the Timer Control Register.
  2. Write the lower 32-bit Comparator Value Register.
  3. Write the upper 32-bit Comparator Value Register.
  4. Set the Comp enable bit and, if necessary, the IRQ enable bit.

Auto-increment Register

This 32-bit register gives the increment value of the Comparator Register when the Auto-increment bit is set in the Timer Control Register. Each Cortex®‑R8 processor core present has its own Auto-increment Register.

If the Comp enable and Auto-increment bits are set when the global counter reaches the Comparator Register value, the comparator is incremented by the auto-increment value, so that a new event can be set periodically.

The global timer is not affected, and continues incrementing.

a  When the Auto-increment and Comp enable bits are set, an IRQ is generated every auto-increment register value.
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