9.4.5 Interrupt interface register descriptions

Descriptions of the registers that each Cortex®‑R8 core interface provides.

Core interface register summary table

Summary of the core interface registers. These registers are word accessible. Any other access is unpredictable.

This table does not reproduce information about registers already described in the ARM® Generic Interrupt Controller Architecture Specification.

Table 9-28 Core interface register summary

Base Name Type Reset Width Description
0x000 ICCICR RW 0x00000000 32 CPU Interface Control Register
0x004 ICCPMR RW 0x00000000 32 Interrupt Priority Mask Registera
0x008 ICCBPR RW 0x3 32 Binary Point Register
0x00C ICCIAR RO 0x000003FF 32 Interrupt Acknowledge Register
0x010 ICCEOIR WO - 32 End Of Interrupt Register
0x014 ICCRPR RO 0x000000FF 32 Running Priority Register
0x018 ICCHPIR RO 0x000003FF 32 Highest Pending Interrupt Register
0x0FC ICCIIDR RO 0x3901243B 32 CPU Interface Implementer Identification Register

CPU Interface Implementer Identification Register

The ICCIIDR Register provides information about the implementer and the revision of the controller.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Base: 0x0FC

Name: ICCIIDR

Type: RO

Reset: 0x3901243B

Width: 32

The following figure shows the ICCIIDR bit assignments.

Figure 9-25 ICCIIDR bit assignments
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The following table shows the ICCIIDR bit assignments

Table 9-29 ICCIIDR bit assignments

Bits Values Name Description
[31:20] 0x390 Part number Identifies the peripheral.
[19:16] 0x1 Architecture version Identifies the architecture version.
[15:12] 0x0 Revision number Returns the revision number of the interrupt controller. The implementer defines the format of this field.
[11:0] 0x43B Implementer Returns the JEP 106 code of the company that implemented the Cortex‑R8 processor interface RTL. It uses the following construct:
[11:8]
JEP 106 continuation code of the implementer.
[7]
0.
[6:0]
JEP 106 code [6:0] of the implementer.
a Only the top four bits of each 8-bit field of the register are in use.
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