12.1.2 AXI3 USER bits

AXI3 USER bits encodings.

Read address channel of AXI master 0, ARUSERM0[9:0]

Bit encodings for ARUSERM0[9:0]

Table 12-2 ARUSERM0[9:0] encodings

Bits Name Description
[9:7] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction
[6] Speculative linefill hint Speculative linefill, used with L2C-310 Cache Controller
[5] Reserved 0b0
[4:1] Inner attributes
0b0000Strongly Ordered
0b0001Device
0b0011Normal Memory Non-Cacheable
0b0110Reserveda
0b0111Write-Back no Write-Allocate
0b1111Write-Back Write-Allocate
[0] Shareable bit
0b0Non-Shareable
0b1Shareable

Read address channel of AXI master 1, ARUSERM1[9:0]

Bit encodings for ARUSERM1[9:0].

Table 12-3 ARUSERM1[9:0] encodings

Bits Name Description
[9:7] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction
[6] Speculative linefill hint Speculative linefill, used with L2C-310 Cache Controller
[5] Reserved 0b0
[4:1] Inner attributes
0b0000Strongly Ordered
0b0001Device
0b0011Normal Memory Non-Cacheable
0b0110Reservedb
0b0111Write-Back no Write-Allocate
0b1111Write-Back Write-Allocate
[0] Shareable bit
0b0Non-Shareable
0b1Shareable

Read address bus of AXI low-latency peripheral, ARUSERMP[9:0]

Bit encodings for ARUSERMP[9:0].

Table 12-4 ARUSERMP[9:0] encodings

Bits Name Description
[9:7] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction
[6:5] Reserved 0b00
[4:1] Inner attributes
0b0000Strongly Ordered
0b0001Device
0b0011Normal Memory Non-Cacheable
0b0110Reservedc
0b0111Write-Back no Write-Allocate
0b1111Write-Back Write-Allocate
[0] Shareable bit
0b0Non-Shareable
0b1Shareable

Write address channel of AXI master 0, AWUSERM0[11:0]

Bit encodings for AWUSERM0[11:0].

Table 12-5 AWUSERM0[11:0] encodings

Bits Name Description
[11:9] Transaction type
0b000Core 0 transaction.
0b010Core 1 transaction.
0b100Core 2 transaction.
0b110Core 3 transaction.
0b001ACP transaction.
[8] Early BRESP Enable bit Indicates that the L2 slave can send an early BRESP answer to the write request. See 12.2.1 Early BRESP.
[7:5] Reserved RAZ.
[4:1] Inner attributes
0b0000Strongly Ordered.
0b0001Device.
0b0011Normal Memory Non-Cacheable.
0b0110Reserved.d
0b0111Write-Back no Write-Allocate.
0b1111Write-Back Write-Allocate.
[0] Shareable bit
0b0Non-Shareable.
0b1Shareable.

Write address channel of AXI master 1, AWUSERM1[11:0]

Bit encodings for AWUSERM1[11:0].

Table 12-6 AWUSERM1[11:0] encodings

Bits Name Description
[11:9] Transaction type
0b000Core 0 transaction.
0b010Core 1 transaction.
0b100Core 2 transaction.
0b110Core 3 transaction.
0b001ACP transaction.
[8] Early BRESP Enable bit Indicates that the L2 slave can send an early BRESP answer to the write request. See 12.2.1 Early BRESP.
[7:5] Reserved RAZ.
[4:1] Inner attributes
0b0000Strongly Ordered.
0b0001Device.
0b0011Normal Memory Non-Cacheable.
0b0110Reserved.e
0b0111Write-Back no Write-Allocate.
0b1111Write-Back Write-Allocate.
[0] Shareable bit
0b0Non-Shareable.
0b1Shareable.

Write address bus of AXI low-latency peripheral, AWUSERMP[11:0]

Bit encodings for AWUSERMP[11:0].

Table 12-7 AWUSERMP[11:0] encodings

Bits Name Description
[11:9] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction
[8:5] Reserved RAZ
[4:1] Inner attributes
0b0000Strongly Ordered
0b0001Device
0b0011Normal Memory Non-Cacheable
0b0110Reservedf
0b0111Write-Back no Write-Allocate
0b1111Write-Back Write-Allocate
[0] Shareable bit
0b0Non-Shareable
0b1Shareable

Write data channel of AXI master 0, WUSERM0[2:0]

Bit encodings for WUSERM0[2:0].

Table 12-8 WUSERM0[2:0] encodings

Bits Name Description
[2:0] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction

Write data channel of AXI master 1, WUSERM1[2:0]

Bit encodings for WUSERM1[2:0].

Table 12-9 WUSERM1[2:0] encodings

Bits Name Description
[2:0] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction

Write data bus of AXI low-latency peripheral, WUSERMP[2:0]

Bit encodings for WUSERMP[2:0].

Table 12-10 WUSERMP[2:0] encodings

Bits Name Description
[1:0] Transaction type
0b000Core 0 transaction
0b010Core 1 transaction
0b100Core 2 transaction
0b110Core 3 transaction
0b001ACP transaction
a If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
b If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
c If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
d If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
e If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
f If Write-Through is used in the MPU, it behaves as normal memory, Non-Cacheable, and its value is 0b0110.
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