A.8.3 AXI low-latency peripheral port signals

Cortex®‑R8 processor AXI low-latency peripheral port signals.

AXI low-latency peripheral clock enable signals

Details of the AXI low-latency peripheral port clock enable signals.

Table A-20 AXI low-latency peripheral clock enable signals

Name Type Source/destination Description
INCLKENMP Input CLK Clock enable
OUTCLKENMP Input Clock enable

AXI low-latency peripheral port read address signals

Details of the AXI low-latency peripheral port read address signals.

Table A-21 AXI low-latency peripheral port read address signals

Name Type Source/destination Description
ARADDRMP[31:0] Output AXI3 low-latency peripheral port Read address
ARBURSTMP[1:0] Output Read address burst type
ARCACHEMP[3:0] Output Read address cache type
ARIDMP[n]a Output Read address ID
ARLENMP[3:0] Output Read address burst length
ARLOCKMP[1:0] Output Read address lock type
ARPROTMP[2:0] Output Read address protection type
ARREADYMP Input Read address ready
ARSIZEMP[1:0] Output Read address burst size
ARUSERMP[9:0] Output Read address transfer attributes, see 12.1.2 AXI3 USER bits
ARVALIDMP Output Read address valid

AXI low-latency peripheral port read data signals

Details of the AXI low-latency peripheral port read data signals.

Table A-22 AXI low-latency peripheral port read data signals

Name Type Source/destination Description
RVALIDMP Input AXI3 low-latency peripheral port Read data valid
RREADYMP Output Read data ready
RIDMP[n]b Input Read data ID
RLASTMP Input Read data last
RDATAMP[31:0] Input Read data
RRESPMP[1:0] Input Read data response

AXI low-latency peripheral port write address signals

Details of the AXI low-latency peripheral port write address signals.

Table A-23 AXI low-latency peripheral port write address signals

Name Type Source/destination Description
AWVALIDMP Output AXI3 low-latency peripheral port Write address valid
AWREADYMP Input Write address ready
AWIDMP[n]c Output Write address ID
AWADDRMP[31:0] Output Write address
AWSIZEMP[1:0] Output Write address burst size
AWLENMP[3:0] Output Write address burst length
AWBURSTMP[1:0] Output Write address burst type
AWCACHEMP[3:0] Output Write address cache type
AWPROTMP[2:0] Output Write address protection type
AWLOCKMP[1:0] Output Write address lock type
AWUSERMP[11:0] Output Write address transfer attributes, see 12.1.2 AXI3 USER bits

AXI low-latency peripheral port write data signals

Details of the AXI low-latency peripheral port write data signals.

Table A-24 AXI low-latency peripheral port write data signals

Name Type Source/destination Description
WVALIDMP Output AXI3 low-latency peripheral port Write data valid
WREADYMP Input Write data ready
WIDMP[n]d Output Write data ID
WLASTMP Output Write data last
WSTRBMP[3:0] Output Write data strobes
WDATAMP[31:0] Output Write data
WUSERMP[2:0] Output Write data transfer attributes, see 12.1.2 AXI3 USER bits

AXI low-latency peripheral port write response signals

Details of the AXI low-latency peripheral port write response signals.

Table A-25 AXI low-latency peripheral port write response signals

Name Type Source/destination Description
BVALIDMP Input AXI3 low-latency peripheral port Write response valid
BREADYMP Output Write response ready
BIDMP[n]e Input Write response ID
BRESPMP[1:0] Input Write response
a You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
b You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
c You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
d You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
e You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [5:0].
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