A.8.4 AXI TCM slave port signals

Cortex®‑R8 processor AXI TCM slave port signals.

AXI TCM slave port clock enable signal

Details of the AXI TCM slave port clock enable signal.

Table A-26 AXI TCM slave port clock enable signal

Name Type Source/destination Description
ACLKENST Input Clock controller Clock bus enable for the AXI bus that enables the AXI interface to operate at integer ratios of the system clock

AXI TCM slave port read address signals

Details of the AXI TCM slave port read address signals.

Table A-27 AXI TCM slave port read address signals

Name Type Source/destination Description
ARVALIDST Input AXI3 device Read address valid
ARREADYST Output Read address ready
ARIDST[n]a Input Read address ID
ARADDRST[31:0] Input Read address
ARSIZEST[1:0] Input Read address burst size
ARLENST[3:0] Input Read address burst length
ARBURSTST[1:0] Input Read address burst type
ARUSERST[2:0] Input Read address transfer attributes
ARCACHEST[3:0] Input Read address cache type
ARLOCKST[1:0] Input Read address lock type
ARPROTST[2:0] Input Read address protection type

AXI TCM slave port read data signals

Details of the AXI TCM slave port read data signals.

Table A-28 AXI TCM slave port read data signals

Name Type Source/destination Description
RVALIDST Output AXI3 device Read data valid
RREADYST Input Read data ready
RIDST[n]b Output Read data ID
RLASTST Output Read data last
RDATAST[63:0] Output Read data
RRESPST[1:0] Output Read data response

AXI TCM slave port write address signal

Details of the AXI TCM slave port write address signals.

Table A-29 AXI TCM slave port write address signals

Name Type Source/destination Description
AWVALIDST Input AXI3 device Write address valid.
AWREADYST Output Write address ready.
AWIDST[n]c Input Write address ID.
AWADDRST[31:0] Input Write address.
AWSIZEST[1:0] Input Write address burst size.
AWLENST[3:0] Input Write address burst length. The maximum burst transfer must correspond to an L1 cache line, that is, 256 bits.
AWBURSTST[1:0] Input Write address burst type.
AWUSERST[2:0] Input Write address transfer attributes.
AWCACHEST[3:0] Input Write address cache type.
AWLOCKST[1:0] Input Write address lock type.
AWPROTST[2:0] Input Write address protection type.

AXI TCM slave port write data signals

Details of the AXI TCM slave port write data signals.

Table A-30 AXI TCM slave port write data signals

Name Type Source/destination Description
WVALIDST Input AXI3 device Write data valid
WREADYST Output Write data ready
WIDST[n]d Input Write data ID
WLASTST Input Write data last
WSTRBST[7:0] Input Write data strobes
WDATAST[63:0] Input Write data

AXI TCM slave port write response signals

Details of the AXI TCM slave port write response signals.

Table A-31 AXI TCM slave port write response signals

Name Type Source/destination Description
BVALIDST Output AXI3 device Write response valid
BREADYST Input Write response ready
BIDST[n]e Output Write response ID
BRESPST[1:0] Output Write response
a You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.
b You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.
c You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.
d You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.
e You can define the number of AXI ID bits on this port using the AXIST_ID_BIT build parameter.
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