11.7.2 Functional grouping of registers

Summary of the macrocell registers arranged by functional group. These functional groups include all the registers.

The functional group register tables include additional information about each register, including:

  • The register access type. This is read-only, write-only, or read and write.
  • The base offset address of the register. The base address of a register is always four times its register number.
  • Additional information about the implementation of the register, where appropriate.

General control and ID registers

The general control and ID registers in numerical order.

Table 11-7 General control and ID registers

Register number Name Base offset Description
1 TRCPRGCTLR 0x004 11.8.1 Programming Control Register
2 TRCPROCSELR 0x008 11.8.2 Processor Select Control Register
3 TRCSTATR 0x00C 11.8.3 Status Register
4 TRCCONFIGR 0x010 11.8.4 Trace Configuration Register
6 TRCAUXCTLR 0x018 11.8.5 Auxiliary Control Register
8 TRCEVENTCTL0R 0x020 11.8.6 Event Control 0 Register
9 TRCEVENTCTL1R 0x024 11.8.7 Event Control 1 Register
11 TRCSTALLCTLR 0x02C 11.8.8 Stall Control Register
12 TRCTSCTLR 0x030 11.8.9 Global Timestamp Control Register
13 TRCSYNCPR 0x034 11.8.10 Synchronization Period Register
14 TRCCCCTLR 0x038 11.8.11 Cycle Count Control Register
15 TRCBBCTLR 0x03C 11.8.12 Branch Broadcast Control Register
16 TRCTRACEIDR 0x040 11.8.13 Trace ID Register

Trace filtering control registers

The trace filtering control registers in numerical order.

Table 11-8 Trace filtering control registers

Derived resource registers

The derived resource registers in numerical order.

These registers control:

  • The two counters, and associated events.
  • The sequencer, and associated state change events.
  • Trigger events.
  • EXTOUT (External Output) events.
  • Extended External Input selection.

Table 11-9 Derived resource registers

Register number Name Base offset Description
64-66 TRCSEQVRn 0x100-0x108 11.8.20 Sequencer State Transition Control Registers 0-2
70 TRCSEQRSTEVR 0x118 11.8.21 Sequencer Reset Control Register
71 TRCSEQSTR 0x11C 11.8.22 Sequencer State Register
72 TRCEXTINSELR 0x120 11.8.23 External Input Select Register
80-81 TRCCNTRLDVRn 0x140-0x144 11.8.24 Counter Reload Value Registers 0-1
84 TRCCNTCTLR0 0x150 11.8.25 Counter Control Register 0
85 TRCCNTCTLR1 0x154 11.8.26 Counter Control Register 1
88-89 TRCCNTVRn 0x160-0x164 11.8.27 Counter Value Registers 0-1

Implementation-specific and identification registers

The implementation-specific and identification registers in numerical order.

Table 11-10 Implementation-specific and identification registers

Register number Name Base offset Description
96 TRCIDR8 0x180 11.8.28 ID Register 8-13
97 TRCIDR9 0x184
98 TRCIDR10 0x188
99 TRCIDR11 0x18C
100 TRCIDR12 0x190
101 TRCIDR13 0x194
112 TRCIMSPEC0 0x1C0 11.8.29 Implementation Specific Register 0
120 TRCIDR0 0x1E0 11.8.30 ID Register 0
121 TRCIDR1 0x1E4 11.8.31 ID Register 1
122 TRCIDR2 0x1E8 11.8.32 ID Register 2
123 TRCIDR3 0x1EC 11.8.33 ID Register 3
124 TRCIDR4 0x1F0 11.8.34 ID Register 4
125 TRCIDR5 0x1F4 11.8.35 ID Register 5

Resource selection registers

The resource selection registers in numerical order.

Table 11-11 Resource selection registers

Register number Name Base offset Description
130-140 TRCRSCTLRn 0x208-0x240 11.8.36 Resource Selection Registers 2-16

Single-shot comparator registers

The Single-shot comparator registers in numerical order.

Table 11-12 Single-shot comparator registers

Register number Name Base offset Description
160-161 TRCSSCCRn 0x280-0x284 11.8.37 Single-Shot Comparator Control Registers 0-1
168-169 TRCSSCSRn 0x2A0-0x2A4 11.8.38 Single-Shot Comparator Status Registers 0-1

OS lock and power control registers

The OS lock and power control registers in numerical order.

Table 11-13 OS lock and power control registers

Register number Name Base offset Description
192 TRCOSLAR 0x300 11.8.39 OS Lock Access Register
193 TRCOSLSR 0x304 11.8.40 OS Lock Status Register
196 TRCPDCR 0x310 11.8.41 Power Down Control Register
197 TRCPDSR 0x314 11.8.42 Power Down Status Register

Comparator registers

The comparator registers in numerical order.

Table 11-14 Comparator registers

Register number Name Base offset Description
256-271 TRCACVRn 0x400-0x43C 11.8.43 Address Comparator Value Registers 0-7
288-303 TRCACATRn 0x480-0x4BC 11.8.44 Address Comparator Access Type Registers 0-7
320-321 TRCDVCVRn 0x500-0x504 11.8.45 Data Value Comparator Value Registers 0-1
352-359 TRCDVCMRn 0x580-0x59C 11.8.46 Data Value Comparator Mask Registers 0-1
384 TRCCIDCVR0 0x600 11.8.48 Context ID Comparator Value Register 0

Integration test registers

The Integration test registers in numerical order.

Table 11-15 Integration test registers

Register number Name Base offset Description
951 Integration Miscellaneous Outputs Register 0xEDC Integration Miscellaneous Outputs Register
952 Integration Miscellaneous Inputs Register 0xEE0 Integration Miscellaneous Inputs Register
953 Integration ATB Identification Register 0xEE4 Integration ATB Identification Register
954 Integration Data ATB Data Register 0xEE8 Integration Data ATB Data Register
955 Integration Instruction ATB Data Register 0xEEC Integration Instruction ATB Data Register
956 Integration Data ATB In Register 0xEF0 Integration Data ATB In Register
957 Integration Instruction ATB In Register 0xEF4 Integration Instruction ATB In Register
958 Integration Data ATB Out Register 0xEF8 Integration Data ATB Out Register
959 Integration Instruction ATB Out Register 0xEFC Integration Instruction ATB Out Register

CoreSight™ management registers

The CoreSight™ management registers in numerical order.

Table 11-16 CoreSight management registers

Register number Name Base offset Description
960 TRCITCTRL 0xF00 11.8.49 Integration Mode Control Register
1000 TRCCLAIMSET 0xFA0 11.8.50 Claim Tag Set Register
1001 TRCCLAIMCLR 0xFA4 11.8.51 Claim Tag Clear Register
1002 TRCDEVAFF0 0xFA8 11.8.52 Device Affinity Register
1004 TRCLAR 0xFB0 11.8.53 Software Lock Access Register
1005 TRCLSR 0xFB4 11.8.54 Software Lock Status Register
1006 TRCAUTHSTATUS 0xFB8 11.8.55 Authentication Status Register
1007 TRCDEVARCH 0xFBC 11.8.56 Device Architecture Register
1010 TRCDEVID 0xFC8 11.8.57 Device ID Register
1011 TRCDEVTYPE 0xFCC 11.8.58 Device Type Register
1012-1019 TRCPIDRn 0xFD0-0xFEC 11.8.59 Peripheral Identification Registers
1020-1023 TRCCIDRn 0xFF0-0xFFC 11.8.60 Component Identification Registers
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.