4.3.16 Cache and TCM Debug Operation Register

The CTDOR describes the access operation required for cache and TCM debug.

Usage constraints
The CTDOR is write accessible in privileged mode only.
Configurations
Available in all configurations.
Attributes
See the c15 register summary, 4.2.8 c15 registers.

The following figure shows CTDOR bit assignments for cache RAMs.

Figure 4-18 CTDOR bit assignments for cache RAMs
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The following table shows the CTDOR bit assignments for cache RAMs.

Table 4-36 CTDOR bit assignments for cache RAMs

Bits Name Function
[31:30] Way select

Indicates the way to select in the cache.

0b00Way 0.
0b01Way 1.
0b10Way 2.
0b11Way 3.
[29:23] - Reserved. RAZ/WI.
[22] Select cache RAMs or TCMs
0b0Use with cache RAMs.
[21] Select tag or data RAMs
0b0Use with tag RAMs.
0b1Use with data RAMs.
[20] Select data or instruction side
0b0Select data side.
0b1Select instruction side.
[19:14] - Reserved. RAZ/WI.
[13:5] Cache index Indicates the cache index.
[4:2] Word in data RAM

Indicates the 32-bit word in the cache line.

Only required if accessing data RAM.

[1] - Reserved. RAZ/WI.
[0] Select read or write operation
0b0Read operation.
0b1Write operation.

The following figure shows the CTDOR bit assignments for TCM RAMs.

Figure 4-19 CTDOR bit assignments for TCMs
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The following table shows the CTDOR bit assignments for TCM RAMs.

Table 4-37 CTDOR bit assignments for TCMs

Bits Name Function
[31:23] - Reserved. RAZ/WI.
[22] Select cache or TCM RAMs
0b1Use with TCMs.
[21] - Reserved. RAZ/WI.
[20] Select data or instruction side
0b0Select data side.
0b1Select instruction side.
[19:2] Address Indicates the address of the TCM RAM.
[1] - Reserved. RAZ/WI.
[0] Select read or write operation
0b0Read operation.
0b1Write operation.

To access the CTDOR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c15, c1, 0 ; Read Cache and TCM Debug Operation Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write Cache and TCM Debug Operation Register

Using the CTDOR

Example showing how to use the Cache and TCM Debug Operation Register (CTDOR).

Corrupting a single bit in word x of a data cache

Assumptions:

  • The data to be corrupted is present in L1, way 1. Ways are numbered 0-3.
  • Word 2. Words are numbered 0-7.
  • The address of the data is stored in r0.

Use the register as follows:

  1. Write the CTDOR:

    MOV r2,     #0x3F00         ; Index mask (high bits)
    ORR r2, r2, #0xE0           ; Index mask (low bits)
    AND r1, r0, r2              ; Index extraction for cache access
    ORR r1, r1, #1<<30          ; Way indication
    ORR r1, r1, #1<<22          ; Cache RAM selection
    ORR r1, r1, #1<<21          ; Data RAM selection
    ORR r1, r1, #0<<20          ; Data side memory selection
    ORR r1, r1, #2<<2           ; Word selection
    ORR r1, r1, #0<<0           ; Read operation
    MCR p15, 0, r1, c15, c1, 0  ; Write CTDOR with operation selected above
  2. The word to corrupt is now stored in c15,0,c1,1 and its ECC chunk in c15,0,c1,2:

    MRC p15, 0, r3, c15, c1, 1  ; Read data
    MRC p15, 0, r4, c15, c1, 3  ; Read ECC chunk (useless in this case)
    ORR r3, r3, #1<<5           ; We want to corrupt bit 5 in read word
    MRC p15, 0, r3, c15, c1, 1  ; Copy corrupted data to CP15 register
    MRC p15, 0, r4, c15, c1, 3  ; Copy corrupted ECC chunk to CP15 register (useless in this case)
  3. Write the CTDOR to write the corrupted word on the data cache:

    ORR r1, r1, #1<<0           ; Write operation
    MCR p15, 0, r1, c15, c1, 0  ; Actual write of corrupted data and chunk to L1 cache
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