10.4.3 External debug interface

External debug interface signals.

The following figure shows the external debug interface signals.

Figure 10-4 External debug interface signals
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Authentication signals

Table showing the valid combinations of authentication signals along with their associated debug permissions.

Table 10-15 Authentication signal restrictions

DBGEN NIDEN Invasive debug permitted Non-invasive debug permitted
0 0 No No
0 1 No Yes
1 0 Yes Yes
1 1 Yes Yes

Debug APB interface

The system can access memory-mapped debug registers through the Cortex®‑R8 processor APB slave port. This APB slave interface supports 32-bit wide data, stalls, and slave-generated aborts.

The following table shows the mapping of PADDRDBG[16:2].

Table 10-16 PADDRDBG[16:2] mapping

Address map Reset domain Component
0x00000-0x00FFF Integration ROM Table.
0x01000-0x0FFFF - Reserved.
0x10000-0x10FFF CPU0 Core 0 debug. See Debug register mapping table for debug resource memory mapping.
0x11000-0x11FFF CPU0 Core 0 PMU. See 10.1 Performance Monitoring Unit for PMU resource mapping.
0x12000-0x12FFF CPU1 Core 1 Debug. See Debug register mapping table for debug resource memory mapping.
0x13000-0x13FFF CPU1 Core 1 PMU. See 10.1 Performance Monitoring Unit for PMU resource mapping.
0x14000-0x14FFF CPU2 Core 2 Debug. See Debug register mapping table for debug resource memory mapping.
0x15000-0x15FFF CPU2 Core 2 PMU. See 10.1 Performance Monitoring Unit for PMU resource mapping.
0x16000-0x16FFF CPU3 Core 3 Debug. See Debug register mapping table for debug resource memory mapping.
0x17000-0x17FFF CPU3 Core 3 PMU. See 10.1 Performance Monitoring Unit for PMU resource mapping.
0x18000-0x18FFF Integration Core 0 CTI.
0x19000-0x19FFF Integration Core 1 CTI.
0x1A000-0x1AFFF Integration Core 2 CTI.
0x1B000-0x1BFFF Integration Core 3 CTI.
0x20000-0x1BFFF - Reserved.
0x1C000-0x1CFFF Integration Core 0 ETM.
0x1D000-0x1DFFF Integration Core 1 ETM.
0x1E000-0x1EFFF Integration Core 2 ETM.
0x1F000-0x1FFFF Integration Core 3 ETM.

The PADDRDBG31 signal indicates the source of the access to the core.

External debug request interface

The external debug request interface signals assert various debug states and indicate debug events.

EDBGRQ

This signal generates a halting debug event by requesting the core to enter debug state. When this occurs, the DSCR[5:2] method of debug entry bits are set to 0b0100. When EDBGRQ is asserted, it must be held until DBGACK is asserted. Failure to do so causes unpredictable behavior of the core.

DBGACK

The core asserts DBGACK to indicate that the system has entered debug state. It serves as a handshake for the EDBGRQ signal. The DBGACK signal is also driven HIGH when the debugger sets the DSCR[10] DbgAck bit to 1.

DBGCPUDONE

DBGCPUDONE is asserted when the core has completed a Data Synchronization Barrier (DSB) as part of the entry procedure to debug state.

The processor asserts DBGCPUDONE only after it has completed all non-debug state memory accesses. Therefore the system can use DBGCPUDONE as an indicator that all memory accesses issued by the core result from operations performed by a debugger.

The following figure shows the Cortex‑R8 processor connections specific to debug request and restart and the CoreSight™ inputs and outputs.

Figure 10-5 Debug request restart-specific connections
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COMMRX and COMMTX

The COMMRX and COMMTX output signals enable interrupt-driven communications over the DTR. By connecting these signals to an interrupt controller, software using the Debug Communications Channel can be interrupted whenever there is new data on the channel or when the channel is clear for transmission:

  • COMMRX is asserted when the CP14 DTR has data for the core to read, and is deasserted when the core reads the data. Its value is equal to the DBGDSCR[30] DTRRX full flag.
  • COMMTX is asserted when the CP14 DTR is ready for write data, and is deasserted when the core writes the data. Its value is equal to the inverse of the DBGDSCR[29] DTRTX full flag.
DBGROMADDR and DBGSELFADDR

Cortex®‑R8 cores have a memory-mapped debug interface, and can access the debug and PMU registers by executing load and store instructions going through the AXI3 bus.

  • DBGROMADDR gives the base address for the ROM table that locates the physical addresses of the debug components.
  • DBGSELFADDR gives the offset from the ROM table to the physical addresses of the registers in the core itself.
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