10.1.2 PMU management registers

The PMU management registers define the standardized set of registers that is implemented by all CoreSight™ components.

The following table shows the contents of the PMU management registers for the Cortex®‑R8 processor debug unit.

Table 10-2 PMU management registers

Offset Register number Access Mnemonic Description
0xD00-0xDFC 832-895 RO - Processor ID Registers
0xE00-0xEF0 854-956 - - RAZ
0xF04-0xF9C 961-999 RAZ - Reserved for Management Register expansion
0xFA0 1000 RW CLAIMSET -
0xFA4 1001 RW CLAIMCLR -
0xFA8-0xFBC 1002-1003 - - RAZ
0xFB0 1004 WO LOCKACCESS -
0xFB4 1005 RO LOCKSTATUS -
0xFB8 1006 RO AUTHSTATUS -
0xFBC-0xFC4 1007-1009 - - RAZ
0xFC8 1010 RO DEVID Device Identifier
0xFCC 1011 RO DEVTYPE -
0xFD0-0xFFC 1012-1023 R - CoreSight™ Identification Registers

Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the corresponding CP15 ID Code Register and Feature ID Register.

The following table shows the offset value, register number, mnemonic, and description that are associated with each Processor ID Register.

Table 10-3 Processor Identifier Registers

Offset (hex) Register number Mnemonic Access Register value Description
0xD00 832 CPUID RO 0x80000n0ma ID Code Register
0xD04 833 CTR RO 0x8333C003 Cache Type Register
0xD08 834 TCMTR RO 0x80010001b 0x00000000c TCM Type Register
0xD0C-0xD1C 835-839 - - - Reserved
0xD20 840 ID_PFR0 RO 0x00000131 Processor Feature Register 0
0xD24 841 ID_PFR1 RO 0x00000001 Processor Feature Register 1
0xD28 842 ID_DFR0 RO 0x00010404 Debug Feature Register 0
0xD2C 843 ID_AFR0 RAZ - Auxiliary Feature Register 0
0xD30 844 ID_MMFR0 RO 0x00110130 Memory Model Feature Register 0
0xD34 845 ID_MMFR1 RO 0x00000000 Memory Model Feature Register 1
0xD38 846 ID_MMFR2 RO 0x01200000 Memory Model Feature Register 2
0xD3C 847 ID_MMFR3 RO 0x00002111 Memory Model Feature Register 3
0xD40 848 ID_ISAR0 RO 0x02101111 Instruction Set Attribute Register 0
0xD44 849 ID_ISAR1 RO 0x13112111 Instruction Set Attribute Register 1
0xD48 850 ID_ISAR2 RO 0x21232141 Instruction Set Attribute Register 2
0xD4C 851 ID_ISAR3 RO 0x01112131 Instruction Set Attribute Register 3
0xD50 852 ID_ISAR4 RO 0x00010142 Instruction Set Attribute Register 4
0xD54 853 ID_ISAR5 RAZ - Instruction Set Attribute Register 5

CoreSight™ Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight™ components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the Cortex‑R8 processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

The following table shows the offset value, register number, value, and description that are associated with each Peripheral Identification Register.

Table 10-4 Peripheral Identification Registers

Offset (hex) Register number Value Description
0xFD0 0x3F4 0x04 Peripheral Identification Register 4
0xFD4 0x3F5 - Reserved
0xFD8 0x3F6 - Reserved
0xFDC 0x3F7 - Reserved
0xFE0 0x3F8 0xB9 Peripheral Identification Register 0
0xFE4 0x3F9 0xB9 Peripheral Identification Register 1
0xFE8 0x3FA 0xrBd Peripheral Identification Register 2
0xFEC 0x3FB 0x00 Peripheral Identification Register 3

The following table shows the offset value, register number, and value that are associated with each Component Identification Register.

Table 10-5 Component Identification Registers

Offset (hex) Register number Value Description
0xFF0 0x3FC 0x0D Component Identification Register 0
0xFF4 0x3FD 0x90 Component Identification Register 1
0xFF8 0x3FE 0x05 Component Identification Register 2
0xFFC 0x3FF 0xB1 Component Identification Register 3

PMU APB interface

PMU register names and corresponding addresses on the APB interface.

Table 10-6 PMU register names and APB addresses

PMU register name Debug APB address
PMU event counter 0 0x000
PMU event counter 1 0x004
PMU event counter 2 0x008
PMU event counter 3 0x00C
PMU event counter 4 0x010
PMU event counter 5 0x014
PMU event counter 6 0x018
PMU event counter 7 0x01C
PMU cycle counter 0x07C
PMU event type 0 0x400
PMU event type 1 0x404
PMU event type 2 0x408
PMU event type 3 0x40C
PMU event type 4 0x410
PMU event type 5 0x414
PMU event type 6 0x418
PMU event type 7 0x41C
PMU count enable set 0xC00
PMU count enable clear 0xC20
PMU interrupt enable set 0xC40
PMU interrupt enable clear 0xC60
PMU overflow flag status 0xC80
PMU software increment 0xCA0
PMU control 0xE04
PMU user enable 0xE08
a n = CLUSTERID input m = core number (0x0 for core 0, 0x1 for core 1, 0x10 for core 2, 0x11 for core 3).
b If TCMs are present.
c If TCMs are not present.
d r represents the variant. For r0p1, this is 0.
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