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Summary of the distributor register.
Registers not described in the distributor register summary table are RAZ/WI. The information in the table does not reproduce information about registers already described in the ARM® Generic Interrupt Controller Architecture Specification.
The ICDIPR and ICDIPTR registers are byte accessible and word accessible. All other registers in the table are word accessible. Any other access is unpredictable.
The offset of this page from PERIPHBASE[31:13] is
Table 9-20 Distributor register summary
||32||Distributor Control Register|
||ICDICTR||RO||Configuration dependent||32||Interrupt Controller Type Register|
||32||Distributor Implementer Identification Register|
||32||Interrupt Set-Enable Registers|
||32||Interrupt Clear-Enable Registers|
||32||Interrupt Set-Pending Registers|
||32||Interrupt Clear-Pending Registers|
||32||Active Bit registers|
||32||Interrupt Priority Registersc|
||32||Interrupt Core Targets Registers|
||ICDICFRn||RW||Implementation dependent||32||Interrupt Configuration Registers|
||32||PPI Status Register|
||32||SPI Status Registers|
||ICDSGIR||WO||-||32||Software Generated Interrupt Register|
||Peripheral Identification [4:0]||RO||Configuration dependent||8||Identification registers|
||Component Identification [3:0]||RO||-||8|
The ICDDCR controls whether the distributor responds to external stimulus changes that occur on SPI and PPI signals.
The following figure shows the ICDDCR bit assignments.
The following table shows the ICDDCR bit assignments.
Table 9-21 ICDDCR bit assignments
The encoding is:
The ICDICTR provides information about the configuration of the interrupt controller.
The following figure shows the ICDICTR bit assignments.
The following table shows the ICDICTR bit assignments.
Table 9-22 ICDICTR bit assignments
The encoding is:
All other values are unused.
|[4:0]||IT lines number||
The encoding is:
All other values are unused.
For systems that support only one core, all ICDIPTRn registers read as zero, and writes are ignored.
0b0for a specific SPI, this interrupt cannot be set pending through the hardware pins or a write to the Set-Pending Register.
Implementation-defined features of the ICDICFR. Each bit-pair describes the interrupt configuration for an interrupt.
The options for each pair depend on the interrupt type as follows:
The bits are read-only:
Interrupt is active-LOW level sensitive.
The LSB of a bit-pair is read-only and is always
You can program the MSB of the bit-pair to alter the triggering
sensitivity as follows:
Interrupt is active-HIGH level sensitive.
There are 31 LSPIs, interrupts 32-62.
The ICDIIDR provides information about the implementer and the revision of the controller.
The following figure shows the ICDIIDR bit assignments.
The following table shows the ICDIIDR bit assignments.
Table 9-23 ICDIIDR bit assignments
||Implementation version||Gives implementation version number|
||Revision number||Returns the revision number of the controller|
The PPI Status Register enables a core to access the status of the inputs on the distributor.
Name: PPI Status
The following figure shows the PPI Status Register bit assignments.
The following table shows the PPI Status Register bit assignments.
Table 9-24 PPI Status Register bit assignments
Returns the status of the PPI[4:0] inputs on the distributor:
PPI and PPI are active LOW.
PPI, PPI, and PPI are active HIGH.
Note:These bits return the actual status of the PPI[4:0] signals. The ICDISPRn and ICDICPRn registers can also provide the PPI[4:0] status but because you can write to these registers then they might not contain the actual status of the PPI[4:0] signals.
The SPI Status Register enable a core to access the status of IRQS[m:0] inputs on the distributor, where m is an increment of 32.
Name: SPI Status
The following figure shows the SPI Status Register bit assignments.
The following table shows the SPI Status Register bit assignments.
Table 9-25 SPI Status Register bit assignments
Returns the status of the IRQS[m:0] inputs on the distributor:
The IRQS that X refers to depends on its bit position and the base address offset of the SPI Status Register as in the following figure shows.
These bits return the actual status of the IRQS signals. The ICDISPRn and ICDICPRn Registers can also provide the IRQS status but because you can write to these registers then they might not contain the actual status of the IRQS signals.
The following figure shows the address map that the distributor provides for the SPIs.
In in this figure the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding core interface. The distributor provides up to seven registers. If you configure the interrupt controller to use fewer than 480 SPIs, then it reduces the number of registers accordingly. For locations where interrupts are not implemented, the distributor:
0x0when it reads from these bits.
The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight™ components. Only bits[7:0] of each register are used.
The Component Identification Registers identify the Cortex®‑R8 processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.
The following table shows the offset value, register number, and description that are associated with each Peripheral Identification Register.
Table 9-26 Peripheral Identification Registers
||Peripheral Identification Register 4|
||Peripheral Identification Register 0|
||Peripheral Identification Register 1|
||Peripheral Identification Register 2|
||Peripheral Identification Register 3|
The following table shows the offset value, register number, and value that are associated with each Component Identification Register.
Table 9-27 Component Identification Registers
|APB offset||Register number||Value||Description|
||Component Identification Register 0|
||Component Identification Register 1|
||Component Identification Register 2|
||Component Identification Register 3|