9.4.4 Distributor register descriptions

Summary of the distributor register.

Registers not described in the distributor register summary table are RAZ/WI. The information in the table does not reproduce information about registers already described in the ARM® Generic Interrupt Controller Architecture Specification.

The ICDIPR and ICDIPTR registers are byte accessible and word accessible. All other registers in the table are word accessible. Any other access is unpredictable.

Distributor register summary table

The offset of this page from PERIPHBASE[31:13] is 0x1000-0x1FFF.

Table 9-20 Distributor register summary

Base Name Type Reset Width Description
0x000 ICDDCR RW 0x00000000 32 Distributor Control Register
0x004 ICDICTR RO Configuration dependent 32 Interrupt Controller Type Register
0x008 ICDIIDR RO 0x0300043B 32 Distributor Implementer Identification Register
0x00C-0x09C - - - - Reserved
0x100-0x13C ICDISERn RW 0x00000000a 32 Interrupt Set-Enable Registers
0x180-0x1BC ICDICERn RW 0x00000000b 32 Interrupt Clear-Enable Registers
0x200-0x23C ICDISPRn RW 0x00000000 32 Interrupt Set-Pending Registers
0x280-0x2BC ICDICPRn RW 0x00000000 32 Interrupt Clear-Pending Registers
0x300-0x33C ICDABRn RO 0x00000000 32 Active Bit registers
0x380-0x3FC - - - - Reserved
0x400-0x4FC ICDIPRn RW 0x00000000 32 Interrupt Priority Registersc
0x7FC - - - - Reserved
0x800-0x9FC ICDIPTRn RWb 0x0000000 32 Interrupt Core Targets Registers
0xBFC - - - - Reserved
0xC00-0xC7C ICDICFRn RW Implementation dependent 32 Interrupt Configuration Registers
0xD00 PPI Status - 0x00000000 32 PPI Status Register
0xD04-0xD3C SPI Status RO 0x00000000 32 SPI Status Registers
0xD80-0xEFC - - - - Reserved
0xF00 ICDSGIR WO - 32 Software Generated Interrupt Register
0xF04-0xFCC - - - - Reserved
0xFD0-0xFEC Peripheral Identification [4:0] RO Configuration dependent 8 Identification registers
0xFF0-0xFFC Component Identification [3:0] RO - 8

Distributor Control Register

The ICDDCR controls whether the distributor responds to external stimulus changes that occur on SPI and PPI signals.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Base: 0x000

Name: ICDDCR

Type: RW

Reset: 0x00000000

Width: 32

The following figure shows the ICDDCR bit assignments.

Figure 9-19 ICDDCR bit assignments
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The following table shows the ICDDCR bit assignments.

Table 9-21 ICDDCR bit assignments

Bits Name Function
[31:1] - Reserved. SBZ.
[0] Enable

The encoding is:

0b0Disables all interrupt control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals.
0b1Enables the distributor to update register locations for interrupts.

Interrupt Controller Type Register

The ICDICTR provides information about the configuration of the interrupt controller.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Base: 0x004

Name: ICDICTR

Type: RO

Reset: Configurationdependent

Width: 32

The following figure shows the ICDICTR bit assignments.

Figure 9-20 ICDICTR bit assignments
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The following table shows the ICDICTR bit assignments.

Table 9-22 ICDICTR bit assignments

Bits Name Function
[31:11]   Reserved. SBZ.
[10] - Reserved. RAZ/WI.
[9:8] - Reserved. SBZ.
[7:5] Core number

The encoding is:

0b000The configuration contains one core.
0b001The configuration contains two cores.
0b010The configuration contains three cores.
0b011The configuration contains four cores.

All other values are unused.

[4:0] IT lines number

The encoding is:

0b00000The distributor provides 32 interruptsd, no external interrupt lines.
0b00001The distributor provides 64 interrupts, 32 external interrupt lines.
0b00010The distributor provides 96 interrupts, 64 external interrupt lines.
0b00011The distributor provides 128 interrupts, 96 external interrupt lines.
0b00100The distributor provides 160 interrupts, 128 external interrupt lines.
0b00101The distributor provides 192 interrupts, 160 external interrupt lines.
0b00110The distributor provides 224 interrupts, 192 external interrupt lines.
0b00111The distributor provides 256 interrupts, 224 external interrupt lines.
0b01000The distributor provides 288 interrupts, 256 external interrupt lines.
0b01001The distributor provides 320 interrupts, 288 external interrupt lines.
0b01010The distributor provides 352 interrupts, 320 external interrupt lines.
0b01011The distributor provides 384 interrupts, 352 external interrupt lines.
0b01100The distributor provides 416 interrupts, 384 external interrupt lines.
0b01101The distributor provides 448 interrupts, 416 external interrupt lines.
0b01110The distributor provides 480 interrupts, 448 external interrupt lines.
0b01111The distributor provides 512 interrupts, 480 external interrupt lines.

All other values are unused.

Interrupt Core Targets Registers

For systems that support only one core, all ICDIPTRn registers read as zero, and writes are ignored.

Note:

If the Processor Target field is set to 0b0 for a specific SPI, this interrupt cannot be set pending through the hardware pins or a write to the Set-Pending Register.

Interrupt Configuration Registers

Implementation-defined features of the ICDICFR. Each bit-pair describes the interrupt configuration for an interrupt.

The options for each pair depend on the interrupt type as follows:

SGI
The bits are read-only and a bit-pair always reads as 0b10.
PPI

The bits are read-only:

PPI[1] and [4]:0b01

Interrupt is active-LOW level sensitive.

PPI[0]:0b01
Interrupt is active-HIGH level sensitive.
PPI[2] and [3]:0b11
Interrupt is rising-edge sensitive.
SPI

The LSB of a bit-pair is read-only and is always 0b1. You can program the MSB of the bit-pair to alter the triggering sensitivity as follows:

0b01

Interrupt is active-HIGH level sensitive.

0b11
Interrupt is rising-edge sensitive.

There are 31 LSPIs, interrupts 32-62.

Distributor Implementer Identification Register

The ICDIIDR provides information about the implementer and the revision of the controller.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Base: 0x008

Name: ICDIIDR

Type: RO

Reset: 0x0300043B

Width: 32

The following figure shows the ICDIIDR bit assignments.

Figure 9-21 ICDIIDR bit assignments
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The following table shows the ICDIIDR bit assignments.

Table 9-23 ICDIIDR bit assignments

Bits Values Name Description
[31:24] 0x04 Implementation version Gives implementation version number
[23:12] 0x00 Revision number Returns the revision number of the controller
[11:0] 0x43B Implementer Implementer number

PPI Status Register

The PPI Status Register enables a core to access the status of the inputs on the distributor.

Usage constraints
A core can only read the status of its own PPI and therefore cannot read the status of PPI for other cores.
Configurations
Available in all configurations.
Attributes

Base: 0xD00

Name: PPI Status

Type: -

Reset: 0x00000000

Width: 32

The following figure shows the PPI Status Register bit assignments.

Figure 9-22 PPI Status Register bit assignments
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The following table shows the PPI Status Register bit assignments.

Table 9-24 PPI Status Register bit assignments

Bits Name Function
[31:16] - Reserved. SBZ.
[15:11] ppi_status

Returns the status of the PPI[4:0] inputs on the distributor:

PPI[4]
nIRQ.
PPI[3]
Private watchdog.
PPI[2]
Private timer.
PPI[1]
nFIQ.
PPI[0]
Global timer.

PPI[1] and PPI[4] are active LOW.

PPI[0], PPI[2], and PPI[3] are active HIGH.

Note:

These bits return the actual status of the PPI[4:0] signals. The ICDISPRn and ICDICPRn registers can also provide the PPI[4:0] status but because you can write to these registers then they might not contain the actual status of the PPI[4:0] signals.
[10:0] - Reserved. SBZ.

SPI Status Registers

The SPI Status Register enable a core to access the status of IRQS[m:0] inputs on the distributor, where m is an increment of 32.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Base: 0xD04-0xD3C

Name: SPI Status

Type: RO

Reset: 0x00000000

Width: 32

The following figure shows the SPI Status Register bit assignments.

Figure 9-23 SPI Status Register bit assignments
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The following table shows the SPI Status Register bit assignments.

Table 9-25 SPI Status Register bit assignments

Bits Name Description
[31:0] spi_status

Returns the status of the IRQS[m:0] inputs on the distributor:

Bit[X] = 0b0
IRQS[X] is LOW.
Bit[X] = 0b1
IRQS[X] is HIGH.

Note:

The IRQS that X refers to depends on its bit position and the base address offset of the SPI Status Register as in the following figure shows.

These bits return the actual status of the IRQS signals. The ICDISPRn and ICDICPRn Registers can also provide the IRQS status but because you can write to these registers then they might not contain the actual status of the IRQS signals.

The following figure shows the address map that the distributor provides for the SPIs.

Figure 9-24 SPI Status Register address map
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In in this figure the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding core interface. The distributor provides up to seven registers. If you configure the interrupt controller to use fewer than 480 SPIs, then it reduces the number of registers accordingly. For locations where interrupts are not implemented, the distributor:

  • Ignores writes to the corresponding bits.
  • Returns 0x0 when it reads from these bits.

Identification registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight™ components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the Cortex®‑R8 processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

The following table shows the offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 9-26 Peripheral Identification Registers

Offset Register number Value Description
0xFD0 1012 0x04 Peripheral Identification Register 4
0xFD4 1013 - Reserved
0xFD8 1014 - Reserved
0xFDC 1015 - Reserved
0xFE0 1016 0x18 Peripheral Identification Register 0
0xFE4 1017 0xBC Peripheral Identification Register 1
0xFE8 1018 0x0B Peripheral Identification Register 2
0xFEC 1019 0x00 Peripheral Identification Register 3

The following table shows the offset value, register number, and value that are associated with each Component Identification Register.

Table 9-27 Component Identification Registers

APB offset Register number Value Description
0xFF0 1020 0x0D Component Identification Register 0
0xFF4 1021 0x90 Component Identification Register 1
0xFF8 1022 0x05 Component Identification Register 2
0xFFC 1023 0xB1 Component Identification Register 3
a The reset value for the registers that contain the SGI and PPI interrupts is implementation defined.
b Not configurable. Reset to 1.
c Only the top four bits of each 8-bit field of the register are in use.
d The distributor always uses interrupts of IDs 0-31 to control any SGIs and PPIs that the interrupt controller might contain.
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