6.4.3 Data cache RAM organization

Organization of the tag RAM and data RAM caches.

Tag RAM

The tag RAMs consist of four ways of up to 512 lines. The width of the RAM depends on the build options selected, and the size of the cache.

The following tables show the tag RAM bits where:

  • The tag RAM bits when ECC is implemented.
  • The tag RAM bits when ECC is not implemented.

Table 6-3 Tag RAM bit descriptions, with ECC

Bit in tag cache line Description
Bits[35:29] ECC code bits
Bits[28:27] Outer attribute
Bit[26] Inner allocate attribute
Bit[25] Dirty bit
Bit[24] Shareable bit
Bit[23] Exclusive bit
Bit[22] Valid bit
Bits[21:0] Tag value

Table 6-4 Tag RAM bit descriptions, no ECC

Bit in tag cache line Description
Bits[28:27] Outer attribute
Bit[26] Inner allocate attribute
Bit[25] Dirty bit
Bit[24] Shareable bit
Bit[23] Exclusive bit
Bit[22] Valid bit
Bits[21:0] Tag value

A cache line is marked as valid by bit[22] of the tag RAM. Each valid bit is associated with a whole cache line, so evictions always occur on the entire line.

The following table shows the tag RAM cache sizes and associated RAM organization, assuming no ECC. For ECC, the width of the tag RAMs must be increased by seven bits.

Table 6-5 Cache sizes and tag RAM organization

Cache size Tag RAM organization
4KB 4 banks 29 bits 32 lines
8KB 4 banks 28 bits 64 lines
16KB 4 banks 27 bits 128 lines
32KB 4 banks 26 bits 256 lines
64KB 4 banks 25 bits 512 lines

Data RAM

Data RAM is organized as eight banks of 32-bit wide lines, or in the instruction cache as four banks of 64-bit wide lines.

This RAM organization means that it is possible to:

  • Perform a cache lookup with one RAM access, all banks selected together. This is done for nonsequential read operations, as shown in the figure for nonsequential read operation performed with one RAM access.
  • Select the appropriate bank RAM for sequential read operations, as shown in the figure for sequential read operation performed with one RAM access.
  • Write a line to the eviction buffer in one cycle, a 256-bit read access.
  • Fill a line in one cycle from the linefill buffer, a 256-bit write access.

The following figure shows a cache lookup being performed on all banks with one RAM access.

Figure 6-1 Nonsequential read operation performed with one RAM access.
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The following figure shows the appropriate bank RAM being selected for a sequential read operation.

Figure 6-2 Sequential read operation performed with one RAM access
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The data RAM organization is optimized for 64-bit read operations, because with the same address, two words on the same way can be selected.

Data RAM sizes depend on the build option selected; that is, without ECC implemented, or with ECC implemented.

Data RAM sizes without ECC implemented

Table showing the organization for instruction caches when ECC is not implemented.

Table 6-6 Instruction cache data RAM sizes, no ECC

Cache size Data RAMs
4KB, 4 1KB ways 4 banks 64 bits 128 lines or 8 banks 32 bits 128 lines
8KB, 4 2KB ways 4 banks 64 bits 256 lines or 8 banks 32 bits 256 lines
16KB, 4 4KB ways 4 banks 64 bits 512 lines or 8 banks 32 bits 512 lines
32KB, 4 8KB ways 4 banks 64 bits 1024 lines or 8 banks 32 bits 1024 lines
64KB, 4 16KB ways 4 banks 64 bits 2048 lines or 8 banks 32 bits 2048 lines

The following table shows the organization for data caches when ECC is not implemented.

Table 6-7 Data cache data RAM sizes, no ECC

Cache size Data RAMs
4KB, 4 1KB ways 8 banks 32 bits 128 lines
8KB, 4 2KB ways 8 banks 32 bits 256 lines
16KB, 4 4KB ways 8 banks 32 bits 512 lines
32KB, 4 8KB ways 8 banks 32 bits 1024 lines
64KB, 4 16KB ways 8 banks 32 bits 2048 lines
Data RAM sizes with ECC implemented

Table showing the organization for the instruction cache when ECC is implemented. ECC error detection adds eight bits for every 64 bits, so four bits are added for each RAM bank.

Table 6-8 Instruction cache data RAM sizes with ECC

Cache size Data RAMs
4KB, 4 1KB ways 4 banks 72 bits 128 lines or 8 banks 36 bits 128 lines
8KB, 4 2KB ways 4 banks 72 bits 256 lines or 8 banks 36 bits 256 lines
16KB, 4 4KB ways 4 banks 72 bits 512 lines or 8 banks 36 bits 512 lines
32KB, 4 8KB ways 4 banks 72 bits 1024 lines or 8 banks 36 bits 1024 lines
64KB, 4 16KB ways 4 banks 72 bits 2048 lines or 8 banks 36 bits 2048 lines

The following table shows the organization for the data cache when ECC is implemented. ECC error detection adds seven bits for every 32 bits, so seven bits are added for each RAM bank.

Table 6-9 Data cache data RAM sizes with ECC

Cache size Data RAMs
4KB, 4 1KB ways 8 banks 39 bits 128 lines
8KB, 4 2KB ways 8 banks 39 bits 256 lines
16KB, 4 4KB ways 8 banks 39 bits 512 lines
32KB, 4 8KB ways 8 banks 39 bits 1024 lines
64KB, 4 16KB ways 8 banks 39 bits 2048 lines

The following table shows the organization of the data cache RAM bits when ECC is implemented.

Table 6-10 Data cache RAM bits, with ECC

RAM bits Description
Bits[39:32] ECC code bits for data [31:0]
Bits[31:0] Data [31:0]
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