2.1.2 Components of the Cortex®‑R8 processor

Functional description of the main components of the Cortex®‑R8 processor.

L1 memory system

The L1 memory system has 64-bit data paths throughout the memory system, export of memory attributes for external memory systems, and separate optional instruction and data caches each with a fixed line length of 32 bytes.

Snoop Control Unit

The SCU connects the Cortex®‑R8 processor cores to the memory system and peripherals through the AXI3 interfaces. The SCU has an optional AXI3 64-bit slave port, the Accelerator Coherency Port (ACP).


The SCU supports L1 data cache coherency, but does not support hardware management of coherency of the instruction caches.

Interrupt controller

The interrupt controller provides support for handling multiple interrupt sources.


The Timers provide the ability to schedule events and trigger interrupts.

Debug and Trace

The debug and trace logic includes support for ARMv7 Debug architecture with an APB slave interface for access to the debug registers.

The debug and trace logic also includes:

  • Performance Monitor Unit (PMU) based on the PMUv1 architecture.
  • Embedded Trace Macrocell (ETM) based on the ETMv4 architecture and dedicated ATB interface per core.
  • Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) for multicore debugging.


The Cortex®‑R8 processor can be configured so that it can be switched, under reset, between a twin-core performance mode and a dual-redundant lock-step mode. This feature imposes extra constraints on the software usage model. ARM provides an init code sequence to guarantee the master core and the redundant core leave reset in exactly the same state.

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