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To prevent the loss of any data that might cause the processor or the system to malfunction, the ECC protects the L1 data cache RAMs, L1 instruction cache RAMs, SCU Tag RAM, Instruction TCM, and Data TCM.
To prevent the loss of any data that might cause the Cortex®‑R8 processor or the system to malfunction, the ECC protects the L1 data cache RAMs, L1 instruction cache RAMs, SCU tag RAM, Instruction TCM, and Data TCM.
The basic ECC scheme for the L1 cache, SCU RAM, and TCM is that any error, either soft or hard, is indicated to the system, and any error detected is stored in an error bank, waiting to be analyzed by the system, and preventing that location from being used.
From the analysis, the errors detected are classified as soft or hard errors. If the errors are hard, the core updates the error bank with this information and the corresponding RAM location is not used by subsequent accesses. There is one error bank for each of the following:
L1 data cache RAMs.
The following table shows the basic scheme, and also the differences where it is part of the core, that is, L1 cache and TCM, or is seen as a peripheral such as the SCU.
Table 7-2 Basic ECC scheme per RAM type
|Correctable error notification to the system, bits[10:9] of the ACTLR cleared||-||-||-|
|Correctable error notification to the system, bits[10:9] of the ACTLR set||Error notificationa||-||Error notificationa|
|Uncorrectable error notification to the system||Error notificationa||Error notificationa||Error notificationa|
|Logging of errors||Up to three entries in the error bank||Up to two entries in the error bank||One entry in the error bank|
|Direct access to the faulty RAM location by the system for full RAM analysis||MBIST||MBIST||MBIST or slave port|
|Direct access to the faulty RAM location by the core itself for single location analysis||CP15 Debug Cache Access Registers||Memory-mapped register in the SCU||CP15 Debug TCM Access Registers|
|Access to the error bank to update it after analysis of the faulty RAM location||CP15||Memory-mapped register in the SCU||CP15|
The direct access to the faulty RAM location by the core for single location analysis also enables errors to be injected so that the error handling mechanism can be checked. This provides a full software support to generate errors on particular locations in the RAM, and then enabling and disabling the ECC after those accesses.
The MBIST interface can be used during WFI. The MBIST controller has some arbitration on the RAMs and can get a clock running in the processor clock module when the MBISTENABLE signal is active, so that flops before and after the RAMs can be activated. Any other MBIST usage while the processor is running is not supported.