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The Cortex®‑R8 processor reset signals enable you to reset parts of your design independantly of one another.
In the following list of reset signals, CN represents the number of configured cores minus one. For example DBGACK[CN:0], if the number of configured cores is 2, CN = 1.
The Cortex‑R8 processor has the following reset signals:
The following reset signals are present for CoreSight™ debug logic:
The following reset signals are present if an ETM is present. The x in the signal name represents 0 for ETM0, 1 for ETM1, 2 for ETM2 or 3 for ETM3:
The following additional reset signals are present if lock-step or split/lock is implemented:
The reset signals in the Cortex‑R8 processor design enable you to reset different parts of the design independently. The following table shows the supported reset combinations in a Cortex‑R8 processor system. [n] refers to the core that receives a reset.
Table 2-1 Reset combinations in a Cortex‑R8 processor system
|Reset signals||Cortex‑R8 processor||Individual cores||Cortex‑R8 processor debug||Individual cores|
|Power up||Software||Power up||Software||Debug||Watchdog flag|
|nSCURESET and nPERIPHRESET||0||0||1||1||1||1||1|
|nCPURESET[CN:0]||All 0||All 0||[n] = 0||[n] = 0||All 1||All 1||All 1|
|nDBGRESET[CN:0]||All 0||All 1||[n] = 0||All 1||All 0||[n] = 0||All 1|
|nWDRESET[CN:0]||All 0||All 0||[n] = 0 or all 1||[n] = 0 or all 1||All 1||All 1||[n] = 0|
You must apply power up, or cold, reset to the Cortex®‑R8 processor when power is first applied to the system. For power up reset, the leading edges, that are the falling edges, of the reset signals do not have to be synchronous to CLK, but the rising edges must be. To ensure correct reset behavior, you must assert the reset signals for at least ten CLK cycles.
If lock-step or split/lock is enabled, you must generate DUALPERIPHCLK, DUALPERIPHCLKEN, and DUALPERIPHCLKOFF as delayed versions of the equivalent primary core signals. Use the same delay as between the primary core and the redundant core.
ARM recommends the following reset sequence:
For a lock-step or split/lock implementation, use the following reset sequence:
Restart the CLK clock and maintain DUALPERIPHCLKOFF HIGH.
SCUCLKOFF and PERIPHCLKOFF are driven LOW. You can maintain these two signals HIGH a few more clock cycles, but this is not required.
This reset applies to an individual core. It initializes the whole logic in a single core, including its debug logic. It is expected to be applied when this core exits from powerdown or dormant state. This reset only applies to configurations where each core is implemented in its own power domain. The x at the end of the signal name represents either the core or ETM ID number.
The reset sequence is as follows:
A core power up reset can be extended to enable its corresponding ETM to be powered down. To wake up from powerdown or dormant mode with the ETM, use the nETMxRESET and ETMxCLKOFF signals in the same way as nCPURESETx and CPUCLKOFFx.
This reset applies to an individual core, without debug logic. It initializes all functional logic in a single core apart from its debug logic. All breakpoints and watchpoints are retained during this individual Warm reset. This reset only applies to configurations where each core is implemented in its own power domain. The x in the signal name represents either the core or ETM ID number.
ARM recommends that you use the reset sequence for the individual core power up reset. To ensure that the debug registers of the individual cores retain their values, the following signals must not be asserted during the reset sequence:
This reset initializes the debug logic in all cores present in the cluster. To perform a Cortex®‑R8 processor debug reset, assert all nDBGRESET signals for a several CLK cycles. CPUCLKOFFx, and ETMxCLKOFF if an ETM is present, must remain deasserted during this reset sequence.
This reset initializes the debug logic in an individual core in the cluster. To perform an individual core debug reset, assert the corresponding nDBGRESETx signal for several CLK cycles. CPUCLKOFFx, and ETMxCLKOFF if the ETM is present, must remain deasserted during this reset sequence.
This reset clears the watchdog flag associated with a specific core. Watchdog functionality is independent of all other core functionality, so this reset is independent of all other resets.