About this book

ARM® Cortex®‑R8 MPCore Technical Reference Manual (TRM) providing reference information on the processor design, implementation, registers, and interfaces. The guide includes documentation on the Memory Protection Unit (MPU), interrupt controller, debug, level 1 and level 2 interfaces. Available as PDF.

Implementation obligations

This book is designed to help you implement an ARM product. The extent to which the deliverables may be modified or disclosed is governed by the contract between ARM and Licensee. There may be validation requirements, which if applicable will be detailed in the contract between ARM and Licensee and which if present must be complied with prior to the distribution of any silicon devices incorporating the technology described in this document. Reproduction of this document is only permitted in accordance with the licences granted to Licensee.

ARM assumes no liability for your overall system design and performance, the verification procedures defined by ARM are only intended to verify the correct implementation of the technology licensed by ARM, and are not intended to test the functionality or performance of the overall system. You or the Licensee will be responsible for performing any system level tests.

You are responsible for any applications which are used in conjunction with the ARM technology described in this document, and in order to minimize risks adequate design and operating safeguards should be provided for by you. ARM's publication of any information in this document of information regarding any third party’s products or services is not an express or implied approval or endorsement of the use thereof.

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:

rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.

Intended audience

This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Cortex®‑R8 processor.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

This chapter introduces the Cortex®‑R8 processor and its features.

Chapter 2 Functional Description

This chapter describes the functionality of the Cortex®‑R8 processor.

Chapter 3 Programmers Model

This chapter describes the programmers model.

Chapter 4 System Control

This chapter describes the system control registers, their structure and operation, and how to use them.

Chapter 5 Floating Point Unit Programmers Model

This chapter describes the programmers model of the optional Floating-Point Unit (FPU).

Chapter 6 Level One Memory System

This chapter describes the L1 memory system.

Chapter 7 Fault Detection

This chapter describes the fault detection features of the Cortex®‑R8 processor.

Chapter 8 Determinism Support

This chapter describes the determinism support features of the Cortex®‑R8 processor.

Chapter 9 Multiprocessing

This chapter describes the multiprocessing features of the Cortex®‑R8 processor, including the SCU.

Chapter 10 Monitoring, Trace, and Debug

This chapter describes the monitoring, trace, and debug features of the Cortex®‑R8 processor.

Chapter 11 Embedded Trace Macrocell

This chapter describes the Embedded Trace Macrocell for the Cortex®‑R8 processor.

Chapter 12 Level Two Interface

This chapter describes the L2 memory interface.

Appendix A Signal Descriptions

This appendix describes the Cortex®‑R8 processor signals. Signal name, direction, and source/destination details are provided for each signal.

Appendix B Cycle Timings and Interlock Behavior

This appendix describes the cycle timings of integer instructions on Cortex®‑R8 processor cores.

Appendix C Revisions

This appendix describes the technical changes between released issues of this book.

Glossary

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.

See the ARM Glossary for more information.

Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the ARM Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.




Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

  • HIGH for active-HIGH signals.

  • LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.

ARM publications
  • ARM® Cortex®‑R8 MPCore Processor Technical Reference Manual (ARM 100400).
  • ARM® Cortex®‑R8 MPCore Processor Configuration and Sign-off Guide (ARM 100401).
  • ARM® Embedded Trace Macrocell Architecture Specification ETMv4 (ARM IHI 0064).
  • ARM® CoreSight™ Architecture Specification (ARM IHI 0029).
  • ARM® CoreSight™ SoC‑400 Technical Reference Manual (ARM DDI 0480).
  • ARM® CoreSight™ SoC‑400 Implementation Guide (ARM DII 0267).
  • ARM® CoreSight™ SoC‑400 Integration Manual (ARM DIT 0037).
  • ARM® CoreSight™ SoC‑400 System Design Guide (ARM DGI 0018).
  • ARM® CoreSight™ SoC‑400 User Guide (ARM DUI 0563).
  • ARM® CoreSight™ DAP-Lite2 Technical Reference Manual (ARM DDI 0316).
  • ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite (ARM IHI 0022).
  • ARM® AMBA® 3 AHB-Lite Protocol Specification (ARM IHI 0033).
  • ARM® AMBA® APB Protocol Specification (ARM IHI 0024).
  • ARM® Design Simulation Model User Guide (ARM DUI 0302).
  • ARM® Generic Interrupt Controller Architecture Specification (ARM IHI 0069).
  • ARM® CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference Manual (ARM DDI 0246).
  • ARM® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 (ARM IHI 0031).
Other publications
This section lists relevant documents published by third parties:
  • 1149.1-2013, IEEE Standard for Test Access Port and Boundary-Scan Architecture (JTAG).
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.