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ARM® Cortex®‑R8 MPCore Technical Reference Manual (TRM) providing reference information on the processor design, implementation, registers, and interfaces. The guide includes documentation on the Memory Protection Unit (MPU), interrupt controller, debug, level 1 and level 2 interfaces. Available as PDF.
This book is designed to help you implement an ARM product. The extent to which the deliverables may be modified or disclosed is governed by the contract between ARM and Licensee. There may be validation requirements, which if applicable will be detailed in the contract between ARM and Licensee and which if present must be complied with prior to the distribution of any silicon devices incorporating the technology described in this document. Reproduction of this document is only permitted in accordance with the licences granted to Licensee.
ARM assumes no liability for your overall system design and performance, the verification procedures defined by ARM are only intended to verify the correct implementation of the technology licensed by ARM, and are not intended to test the functionality or performance of the overall system. You or the Licensee will be responsible for performing any system level tests.
You are responsible for any applications which are used in conjunction with the ARM technology described in this document, and in order to minimize risks adequate design and operating safeguards should be provided for by you. ARM's publication of any information in this document of information regarding any third party’s products or services is not an express or implied approval or endorsement of the use thereof.
n identifier indicates the revision status of the product described in this book, for example, r
|r||Identifies the major revision of the product, for example, r1.|
|p||Identifies the minor revision or modification status of the product, for example, p2.|
This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Cortex®‑R8 processor.
This book is organized into the following chapters:
This chapter introduces the Cortex®‑R8 processor and its features.
This chapter describes the functionality of the Cortex®‑R8 processor.
This chapter describes the programmers model.
This chapter describes the system control registers, their structure and operation, and how to use them.
This chapter describes the programmers model of the optional Floating-Point Unit (FPU).
This chapter describes the L1 memory system.
This chapter describes the fault detection features of the Cortex®‑R8 processor.
This chapter describes the determinism support features of the Cortex®‑R8 processor.
This chapter describes the multiprocessing features of the Cortex®‑R8 processor, including the SCU.
This chapter describes the monitoring, trace, and debug features of the Cortex®‑R8 processor.
This chapter describes the Embedded Trace Macrocell for the Cortex®‑R8 processor.
This chapter describes the L2 memory interface.
This appendix describes the Cortex®‑R8 processor signals. Signal name, direction, and source/destination details are provided for each signal.
This appendix describes the cycle timings of integer instructions on Cortex®‑R8 processor cores.
This appendix describes the technical changes between released issues of this book.
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
See the ARM Glossary for more information.
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
The signal conventions are:
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
HIGH for active-HIGH signals.
LOW for active-LOW signals.
At the start or end of a signal name denotes an active-LOW signal.
This book contains information that is specific to this product. See the following documents for other relevant information.