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The ARM® architecture defines a set of memory types with characteristics that are suited to particular devices.
There are three mutually exclusive memory type attributes:
MPU memory regions must each be assigned a memory type attribute. in the following table shows a summary of the memory types.
Table 8-1 Memory attributes summary
|Memory type attribute||Shareable or Non-Shareable||Other attributes||Description|
|Strongly Ordered||-||-||All memory accesses to Strongly-Ordered memory occur in program order. All Strongly-Ordered accesses are assumed to be Shareable.|
|Device||Shareable||-||For memory-mapped peripherals that several cores share.|
|Non-Shareable||-||For memory-mapped peripherals that only a single core uses.|
|Normal||Shareable||Non-Cacheable Write-Back Cacheable||For normal memory that is Shareable between several cores.|
|Non-Shareable||Non-Cacheable Write-Back Cacheable||For normal memory that only a single core uses.|
For more information on memory attributes and types, memory barriers, and ordering requirements for memory accesses, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
The memory system contains a store buffer. This helps to improve the throughput of accesses to Normal type memory.
Because of the ordering rules that they must follow, accesses to other types of memory typically have a lower throughput and higher latency than accesses to Normal memory. In particular, reads from Device or Strongly-Ordered memory must first drain the store buffer of all writes to Device or Strongly-Ordered memory:
Similarly, when the core is accessing Strongly-Ordered or Device type memory, its response to interrupts is modified, and the interrupt response latency is longer.
To ensure optimum performance, you must understand the architectural semantics of the different memory types. Use Device memory type for appropriate memory regions, typically peripherals, and only use Strongly-Ordered memory type for memory regions where it is essential.