2.5.5 AXI TCM slave port

The AXI TCM slave port enables AXI masters, including the AXI master port of the processor if connected externally, to access data and instruction TCMs on the AXI system bus. You can use this for Direct Memory Access (DMA) to and from the TCM RAMs, and for software test of the TCM.

The following table shows the AXI TCM Slave Port attributes.

Table 2-5 AXI TCM Slave Port attributes

Attribute Format
Write acceptance capability

2

Read acceptance capability

2

The AXI TCM slave port has optional ECC protection on data, and provides parity on control bits.

The AXI TCM slave port also has optional inline single ECC error correction on read accesses for DTCM and ITCM.

The AXI slave port accesses have lower priority than the Load Store Unit (LSU) or PreFetch Unit (PFU) accesses. The MPU does not check accesses from the AXI TCM slave.

The AXI TCM slave port is 64 bits wide and conforms to the AXI standard. Within the AXI standard, the slave port uses the AWUSERST and ARUSERST signals as two separate chip select input signals to enable access as the following table shows.

Table 2-6 AXI TCM slave port access

AxUSERST[2:0] Access
0b000 Instruction TCM for core 0
0b001 Data TCM for core 0
0b010 Instruction TCM for core 1
0b011 Data TCM for core 1
0b100 Instruction TCM for core 2
0b101 Data TCM for core 2
0b110 Instruction TCM for core 3
0b111 Data TCM for core 3

The external AXI system must generate the chip select signals. The AXI TCM slave interface routes the access to the required RAM.

Configurable AXI ID bits

You can configure the number of bits for the AXI IDs in the AXI TCM slave port at the implementation level. This number must be greater than or equal to 1.

Supported AXI transfers

Accesses supported by the AXI TCM slave port.

The following tables show the accesses that the AXI TCM slave port supports.

Table 2-7 Doubleword accesses, aligned on 64-bit address

Signal Access
AxSIZEST[2:0] 0x3
AxLENST[3:0] Any
AxBURSTST[1:0] Any (FIXED, INCR, or WRAP)
AxADDRST[31:0] 0x0

Table 2-8 Single word accesses, aligned on 32-bit address

Signal Access
AxSIZEST[2:0] 0x2
AxLENST[3:0] 0x0
AxBURSTST[1:0] Ignored
AxADDRST[31:0] 0x0

Table 2-9 Single halfword accesses, aligned on 16-bit address

Signal Access
AxSIZEST[2:0] 0x1
AxLENST[3:0] 0x0
AxBURSTST[1:0] Ignored
AxADDRST[31:0] 0x0

Table 2-10 Single byte accesses

Signal Access
AxSIZEST[2:0] 0x0
AxLENST[3:0] 0x0
AxBURSTST[1:0] Ignored

Any other AXI accesses, such as unaligned or multiple accesses, result in a slave error, that is, xRESPST[1:0] = 0b10.

The AXI TCM slave port also supports the following accesses, but with limited bandwidth:

  • Doubleword accesses to the DTCM or ITCM where all byte strobes are not set, that is, WSTRBST[7:0] is not 0xFF.
  • Word accesses to the DTCM where all byte strobes are not set, that is, WSTRBST[7:0] is not 0x0F or 0xF0.
  • Word accesses to the ITCM, regardless of the byte strobe setting.
  • Halfword accesses to the DTCM or ITCM, regardless of the byte strobe setting.
  • Byte accesses to the DTCM or ITCM.

In the following cases, the AXI TCM slave port also gives a slave error:

  • Nonsingle byte, halfword, or word accesses, that is, AxSIZEST[1:0] is not 0x3 and AxLENST[3:0] is not 0x0.
  • The address for the TCM corresponding to AxUSERST[1:0] exceeds the targeted TCM size, defined by the DTCMRR or ITCMRR register.
  • The access is targeting a TCM of a core that is not present.

The AxLOCKST, AxCACHEST, and AxPROTST signals are not implemented on the AXI TCM slave port. This means that the AXI TCM slave interface does not support locked or exclusive accesses. There is no exclusive monitor. If any master attempts an exclusive read, the AXI TCM slave port returns an OKAY response instead of an EXOKAY response. The master can treat this as an error condition indicating that the exclusive access is not supported. ARM recommends that the master does not perform the write portion of this exclusive operation.

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