8.2.3 Region attributes

Each region has several attributes associated with it. These control how a memory access is performed when the core accesses an address that falls within a given region.

The attributes are:

  • Memory type, one of:

    • Strongly Ordered.

    • Device.
    • Normal.
  • Shareable or Non-Shareable.
  • Non-Cacheable.
  • Write-Back Write Allocate.

The Region Access Control Registers use five bits to encode the memory region type. These are the TEX[2:0], C, and B bits. in the following table shows the mapping of these bits to memory region attributes.

Note:

In earlier versions of the architecture, the TEX, C, and B bits were known as the Type Extension, Cacheable and Bufferable bits. These names no longer adequately describe the function of the B, C, and TEX bits.

In addition, the MPU Region Access Control Registers contain the Shareable bit, S. This bit usually determines whether the memory region is Shareable (0b1) or Non-Shareable (0b0). However, in some cases, the Shareable attribute is forced by other attributes, for example, Strongly-Ordered memory types are always Shareable.

Table 8-2 TEX[2:0], C, and B encodings

TEX[2:0] C B Description Memory type Shareable?
0b000 0b0 0b0 Strongly Ordered Strongly Ordered Shareable
0b000 0b0 0b1 Shareable Device Device Shareable
0b000 0b1 0bX Reserved - -
0b001 0b0 0b0 Outer and Inner Non-Cacheable Normal S bit.a
0b001 0b0 0b1 Reserved - -
0b001 0b1 0b0
0b001 0b1 0b1 Outer and Inner Write-Back, Write-Allocate Normal S bita
0b010 0b0 0b0 Non-Shareable Device Device Non-Shareable
0b010 0b0 0b1 Reserved - -
0b010 0b1 0bX
0b011 0bX 0bX
0b1BB 0bA 0bA

Cacheable memory. See the Cacheable memory policies for the encoding for these bits.

0bAA
Inner policy
0bBB
Outer policy
Normal S bita

Cacheable memory policies

When TEX[2] == 0b1, the memory region is cacheable memory, and the rest of the encoding defines the Inner and Outer cache policies.

TEX[1:0]
Defines the Outer cache policy.
C, B
Defines the Inner cache policy.

The same encoding is used for the Outer and Inner cache policies. in the following table shows the encoding.

Table 8-3 Inner and Outer cache policy encoding

Memory attribute encoding Cache policy
0b00 Non-Cacheable
0b01 Write-Back, Write-Allocate
0b1X Reserved

When the processor performs a memory access through its AXI3 bus master interface:

  • The Inner attributes are indicated on the AxUSERMx signals.
  • The Outer attributes are indicated on the AxCACHEMx signals.

For more information on region attributes, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.

a Region is Shareable if S == 0b1, and Non-Shareable if S == 0b0
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