7.6 Lock-step

Lock-step mode requires the Cortex®‑R8 processor to be implemented with a second, redundant copy of the cpu_noram, scu_noram, and axis modules. This provides redundancy in the logic without duplicating the RAMs that are protected by ECC.

The following figure shows how lock-step is implemented.

Figure 7-1 Lock-step
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Because the dual-redundant logic has a significant impact on the area, not duplicating the RAMs minimizes this impact. Both copies of the logic run in parallel, although offset in time, and the outputs are compared to detect errors. There are two sets of comparators:

All outputs of the noram modules are compared, except for the debug, MRP, ETM, and MBIST signals.


COMPENABLE and COMPFAULT are global for both the core and SCU comparators.
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