1.6.1 Split/lock

If the Cortex®‑R8 processor has only two cores and the Split/lock infrastructure implemented, the two core cluster can operate in either split mode or locked mode.

Split mode
Operates as a multiprocessing configuration, with both cores capable of processing, by maintaining L1 data cache coherency. Each core uses its dedicated cache RAM. Also known as performance mode.
Locked mode
Operates in lock-step mode. The second core works as redundant logic for the primary core logic, and the SCU logic, but not the ETM logic if the ETM is present. The redundant core-side cache RAM remains implemented but not used.

You can select the usage mode with the SAFEMODE input signal. This input can be changed only while the two core processor is held in reset and must remain stable when out of reset.

For more information about how to make a change in your system, contact your system integrator.

If you are implementing a Split/lock configuration, contact ARM for more information.

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