5.5.2 Floating-Point Status and Control Register

The FPSCR provides user-level control and status of the FPU.

Usage constraints
There are no usage constraints.
Configurations
Available in all FPU configurations.
Attributes
See the FPU system registers summary, 5.4 FPU register summary.

The following figure shows the FPSCR bit assignments.

Figure 5-2 FPSCR bit assignments
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The following table shows the FPSCR bit assignments.

Table 5-5 FPSCR bit assignments

Bits Name Function
[31] N Set to 0b1 if a comparison operation produces a less than result.
[30] Z Set to 0b1 if a comparison operation produces an equal result.
[29] C Set to 0b1 if a comparison operation produces an equal, greater than, or unordered result.
[28] V Set to 0b1 if a comparison operation produces an unordered result.
[27] - Reserved. UNK/SBZP.
[26] AHP

Alternative half-precision control bit:

0b0IEEE half-precision format selected.
0b1Alternative half-precision.
[25] DN

Default NaN mode control bit:

0b0NaN operands propagate through to the output of a floating-point operation.
0b1Any operation involving one or more NaNs returns the Default NaN.

Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.

[24] FZ

Flush-to-zero mode control bit:

0b0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
0b1Flush-to-zero mode enabled.

Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.

[23:22] RMode

Rounding Mode control field:

0b00Round to nearest (RN) mode.
0b01Round towards plus infinity (RP) mode.
0b10Round towards minus infinity (RM) mode.
0b11Round towards zero (RZ) mode.

Advanced SIMD arithmetic always uses the Round to nearest setting, regardless of the value of the RMode bits.

[21:20] Stride

Stride control used for backwards compatibility with short vector values.

See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.

[19] - Reserved. UNK/SBZP.
[18:16] Len

Vector length, used for backwards compatibility with short vector values.

See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.

[15:8] - Reserved. UNK/SBZP.
[7] IDC Input Denormal cumulative exception flag.a
[6:5] - Reserved. UNK/SBZP.
[4] IXC Inexact cumulative exception flag.a
[3] UFC Underflow cumulative exception flag.a
[2] OFC Overflow cumulative exception flag.a
[1] DZC Division by Zero cumulative exception flag.a
[0] IOC Invalid Operation cumulative exception flag.a

You can access the FPSCR with the following VMSR instructions:

VMRS <Rd>, FPSCR ; Read Floating-Point Status and Control Register
VMSR FPSCR, <Rt> ; Write Floating-Point Status and Control Register
a The exception flags, bit[7], and bits[4:0] of the FPSCR are exported on the FPUFLAGS output so they can be monitored externally to the processor, if necessary.
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