11.8.31 ID Register 1

The TRCIDR1 indicates the basic architecture of the Cortex®‑R8 processor ETM.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Register number: 121

Base offset 0x1E4

Name: TRCIDR1

Type: RO

Reset: 0x4100F400

The following figure shows the TRCIDR1 bit assignments.

Figure 11-40 TRCIDR1 bit assignments
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The following table shows the TRCIDR1 bit assignments.

Table 11-52 TRCIDR1 bit assignments

Bits Name Function
[31:24] DESIGNER

Indicates the designer of the trace unit:

0x41ASCII code for A, indicating ARM®.
[23:16] - Reserved. RAZ/WI.
[15:12] - Reserved. RAO/WI.
[11:8] TRCARCHMAJ

Major trace unit architecture version number:

0b0100ETMv4.
[7:4] TRCARCHMIN

Minor trace unit architecture version number:

0b0000Minor revision 0.
[3:0] REVISION

Implementation revision number:

0b0000Implementation revision 0.
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