|Non-Confidential||PDF version||ARM 100400_0001_03_en|
|Home > Floating Point Unit Programmers Model > FPU register descriptions > Floating-Point Exception Register|
The FPEXC Register provides global enable control of the Advanced SIMD and VFP extensions.
The following figure shows the FPEXC Register bit assignments.
The following table shows the FPEXC Register bit assignments.
Table 5-6 FPEXC Register bit assignments
This bit reads-as-zero and ignores writes.
The Cortex®‑R8 processor FPU never requires asynchronous exception handling.
EN bit is cleared to
Defined synchronous instruction exceptional flag:
DEX bit is cleared to
You can access the FPEXC Register with the following
VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register