5.5.3 Floating-Point Exception Register

The FPEXC Register provides global enable control of the Advanced SIMD and VFP extensions.

Usage constraints
Accessible in all FPU configurations, with restrictions.
Configurations
Available in all FPU configurations.
Attributes
See the FPU system registers summary, 5.4 FPU register summary.

The following figure shows the FPEXC Register bit assignments.

Figure 5-3 FPEXC Register bit assignments
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The following table shows the FPEXC Register bit assignments.

Table 5-6 FPEXC Register bit assignments

Bits Name Function
[31] EX

Exception bit:

This bit reads-as-zero and ignores writes.

The Cortex®‑R8 processor FPU never requires asynchronous exception handling.

[30] EN

Enable bit:

0b0VFP extension is disabled.
0b1VFP extension is enabled and operates normally.

The EN bit is cleared to 0b0 at reset.

[29] DEXa

Defined synchronous instruction exceptional flag:

0b0No exception has occurred.
0b1Attempt to perform a VFP vector operation has been trappedb.

The DEX bit is cleared to 0b0 at reset.

[28:26] - Reserved. RAZ/WI.
[25:0] - Reserved. UNK/SBZP.

You can access the FPEXC Register with the following VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register
a In single-precision only configurations, this bit is not set for any double-precision operations, regardless of whether they are vector operations or not.
b The Cortex‑R8 processor FPU hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is nonzero result in the FPSCR.DEX bit being set and a synchronous Undefined instruction exception being taken. You can use software to emulate the short vector feature, if necessary.
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