4.3.5 Cache Size ID Register

The CCSIDR provides information about the architecture of the caches selected by CSSELR.

Usage constraints
The CCSIDR is only accessible in privileged mode.
Available in configurations with caches implemented. If caches are not implemented, the value of this register is unknown.
See the c0 register summary, 4.2.1 c0 registers.

The following figure shows the CCSIDR bit assignments.

Figure 4-5 CCSIDR bit assignments
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The following table shows the CCSIDR bit assignments.

Table 4-22 CCSIDR bit assignments

Bits Name Function
[31] WT

Indicates support available for Write-Through:

0b0Write-Through support not available.
[30] WB

Indicates support available for Write-Back:

0b0Write-Back support not available.
0b1Write-Back support available.
[29] RA

Indicates support available for read allocation:

0b0Read allocation support not available.
0b1Read allocation support available.
[28] WA

Indicates support available for write allocation:

0b0Write allocation support not available.
0b1Write allocation support available.
[27:13] NumSets

Indicates number of sets:

0x1F4KB cache size.
0x3F8KB cache size.
0x7F16KB cache size.
0xFF32KB cache size.
0x1FF64KB cache size.
[12:3] Associativity

Indicates number of ways:

Four ways.
[2:0] LineSize

Indicates number of words:

0b001Eight words per line.

To access the CCSIDR, read the CP15 register with:

MRC p15, 1, <Rd>, c0, c0, 0 ; Read current Cache Size Identification Register

If the CSSELR reads the instruction cache values and caches are implemented, bits[31:28] are 0b0010.

If the CSSELR reads the data cache values and caches are implemented, bits[31:28] are 0b0111.

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