11.3 Interfaces

A Cortex®‑R8 processor ETM has two ATB interfaces, an APB interface, a processor trace interface, and a test interface. There are also a number of other miscellaneous interface signals that configure ETM, trace, and debug options.


Two ATB interfaces, one 32 bits, and one 64 bits wide, used for trace output from the macrocell. These interfaces have handshaking signals that indicate when trace data is valid and when the receiving component is ready to accept data. There are also signals to request and acknowledge a flush of the trace information and to indicate when a trigger condition has occurred.

See the ARM® AMBA® 4 ATB Protocol Specification ATBv1.0 and ATBv1.1 for more information about these interfaces.


An APB interface that provides access to the programmable registers in the ETM and connects to the system Debug APB. This interface is used to configure the ETM for a trace session.

See the ARM® AMBA® 4 ATB Protocol Specification ATBv1.0 and ATBv1.1 for more information about this interface.

Processor trace

The Cortex‑R8 processor passes its execution information to the ETM over the processor trace interface. This interface provides both instruction and data execution history and contains address, data, and control information. The information carried on the control bus includes:

  • The number of instructions executed in the same cycle.
  • Changes in program flow.
  • The current core instruction state.
  • The addresses of memory locations accessed by load and store instructions.
  • The data values transferred by load and store instructions.
  • The type, direction, and size of a transfer.
  • Condition code information.
  • Exception information.
  • Current context ID.

There is also a context ID bus that indicates the current context ID value of the core.

This interface also includes:

  • The ETMEVENT bus.
  • Wait for interrupt state information signals.
  • A signal from the ETM to power up the interface.

The ETM has other interface signals that:

  • Configure the ETM.
  • Input and output external resource information that controls triggering and filtering of the trace stream.
  • Control which core is enabled, as the trace source, on the processor trace interface of the ETM.
  • Enable invasive and non-invasive debug.

This interface contains the scan enable signal used in production testing of the ETM.

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