11.8.41 Power Down Control Register

The TRCPDCR requests the system power controller to keep the Cortex®‑R8 processor ETM powered up.

Usage constraints
There are no usage constraints.
Available in all configurations.

Register number: 196

Base offset 0x310


Type: RW

Reset: 0x00000000

The following figure shows the TRCPDCR bit assignments.

Figure 11-50 TRCPDCR bit assignments
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The following table shows the TRCPDCR bit assignments.

Table 11-63 TRCPDCR bit assignments

Bits Name Function
[31:4] - Reserved. RAZ/WI.
[3] PU

Power up request, to request that power to the Cortex‑R8 processor ETM and access to the trace registers is maintained:

0b0Power not requested.
0b1Power requested.

This bit is reset to 0b0 on a trace unit reset.

[2:0] - Reserved. RAZ/WI.
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