11.8.17 ViewData Main Control Register

The TRCVDCTLR controls data trace filtering.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 40

Base offset 0x0A0

Name: TRCVDCTLR

Type: RW

Reset: -

The following figure shows the TRCVDCTLR bit assignments.

Figure 11-21 TRCVDCTLR bit assignments
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The following table shows the TRCVDCTLR bit assignments.

Table 11-33 TRCVDCTLR bit assignments

Bits Name Function
[31:11] - Reserved. RAZ/WI.
[10] PCREL

Controls tracing of data for transfers that are relative to the Program Counter (PC):

0b0Tracing of PC-relative transfers is unaffected.
0b1Do not trace either the address or value portions of PC-relative transfers.
[9:8] SPREL

Controls tracing of data for transfers that are relative to the Stack Pointer (SP):

0b00Tracing of SP-relative transfers is unaffected.
0b01Reserved.
0b10Do not trace the address portion of SP-relative transfers. A P1 data address element is generated if data value tracing is enabled.
0b11Do not trace either the address or value portions of SP-relative transfers.
[7] TYPE

Selects the resource type:

0b0Single selected resource.
0b1Boolean combined resource pair.
[6:4] - Reserved. RAZ/WI.
[3:0] SEL

Selects the resource number, based on the value of TYPE:

When TYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

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