6.1.1 Data cache policy

Memory regions that are cached in L1 data cache.

The following memory regions are cached in L1 data cache:

  • Normal memory, Write-Back, Non-Shareable.
  • Normal memory, Write-Back, Shareable if multiprocessing is enabled.

Note:

The Write-Through cache policy is not supported. The Memory Reconstruction Port (MRP) provides a way to rebuild step-by-step memory accesses.
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