10.1.3 Performance monitoring events

The Cortex®‑R8 processor implements the ARMv7‑A and ARMv7‑R architectural events. The PMU provides an additional set of Cortex‑R8 processor core-specific events.

The ETM accepts 64 events:

  • Four events from the CTI.
  • Four events are spare pins tied off at the ETM input level.
  • 56 events from the Cortex‑R8 processor, and visible externally through the PMUEVENTx bus, where n is 0, 1, 2 or 3.

The ETM can export two signals that are connected to the processor PMU. These signals are ETMEXTOUT[1] and ETMEXTOUT[2] events. See Chapter 11 Embedded Trace Macrocell for more information about the ETMEXTOUT signals from the ETM.

The following table shows the Cortex‑R8 processor events, with their associated event number, and position in the PMUEVENT bus.

Table 10-7 Cortex‑R8 processor events

Event Description Position in PMUEVENT bus
Common events  
0x00 Software increment [0]
0x01 Instruction cache miss [1]
0x03 Data cache miss [2]
0x04 Data cache access [3]
0x06 Data read [4]
0x07 Data write [5]
0x08 Instruction architecturally executed [11:6]
0x09 Exception taken [12]
0x0A Exception returns [13]
0x0B Write context ID [14]
0x0C Software change of PC [15]
0x0D Immediate branch [16]
0x0E Procedure return, other than exception return [17]
0x0F Unaligned [18]
0x10 Branch mispredicted or not predicted [19]
0x11 Cycle count Not applicable
0x12 Predictable branches [20]
0x14 Instruction cache access [21]
ETM events  
0x40 ETMEXTOUT[1] Not applicable
0x41 ETMEXTOUT[2] Not applicable
Determinism events
0x50 Number of cycles IRQs are interrupted [22]
0x51 Number of cycles FIQs are interrupted [23]
ECC events
0x60 Detected ECC errors on any RAM Not exported
0x61 Parity error on PRED [24]
0x62 Parity error on BTAC [25]
0x63 Detected ECC errors on ITCM [26]
0x64 Detected ECC errors on DTCM [27]
0x65 Detected ECC errors on instruction cache [28]
0x66 Detected ECC errors on data cache [29]
0x67 Correctable ECC errors on any bus Not exported
0x68 Correctable ECC errors on slave bus, data write channel [30]
0x69 Correctable ECC errors on peripheral master bus, data read channel [31]
0x6A Correctable ECC errors on master 0 bus, data read channel [32]
0x6B Correctable ECC errors on master 1 bus, data read channel [33]
0x6C Detected ECC errors on SCU RAM [34]
0x6D Correctable ECC errors on AXI TCM port [48]
0x6E Correctable ECC errors on local AXI fast peripheral port [49]
Software events
0x80 STREX passed [35]
0x81 STREX failed [36]
0x82 Literal pool in TCM region [37]
Microarchitecture events
0x90 DMB stall [38]
0x91 ITCM access [39]
0x92 DTCM access [40]
0x93 Data eviction [41]
0x94 SCU coherency operation (CCB request) [42]
0x95 Instruction cache dependent stall [43]
0x96a Data cache dependent stallb [44]
0x97a Non-Cacheable no peripheral dependent stallc [45]
0x98a Non-Cacheable peripheral dependent stalld [46]
0x99a Data cache high priority dependent stalle [47]
0x9A Accesses to AXI fast peripheral port (reads and writes) [50]
Reserved
- Reserved, tied LOW [55:51]

Note:

You can choose whether these events are enabled or not, and exported or not, using the PMCR Register. See the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition. For a fault-tolerant system, ECC events must be exported for more visibility. To achieve this, there are some specific ECC notification signals. See Chapter 7 Fault Detection for more information.
a  This counter is mostly used when QoS is enabled. The core issue stage is stalled and it contains at least one instruction that it cannot dispatch.
b The counter counts stalls on AXI M0 with low-priority cacheable traffic.
c The counter counts stalls on AXI M0 or M1 with low-priority NC/SO/Dev.
d The counts stall on AXI MP with high-priority SO/DEV.
e The counts stall on AXI M1 with high-priority when a local SRAM is in use.
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