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The Cortex®‑R8 processor supports parallel instruction execution. This means that the macrocell is capable of tracing two instructions per cycle.
Although the ViewInst is evaluated for each instruction as required, the macrocell does not trace one instruction without the other. In other words, if one instruction is specified to be traced, the instruction it is paired with is always traced as well. If ViewData is active, any data associated with the paired instruction is also traced. If ViewData selects only one transfer of a multiple load or store, both transfers which are issued by the core as a 64-bit transfer are traced.