7.2.6 Performance impact

In an error-free system, the major performance impact is the cost of the read-modify-write scheme for nonfull stores in the data side. If the store buffer does not have a complete ECC chunk, it must read the word to be able to compute the check bits. The data can then be written in the RAM. This additional read can have a negative impact in performance because it prevents the slot from being used for another write.

The out-of-order and outstanding capabilities of the L1 memory system mask part of the additional read, and it is negligible for most codes. However, ARM recommends that you use as few cacheable STRB/STRH instructions as possible to reduce the performance impact.


There might be a frequency impact because XOR trees are added on the data returned from the RAMs.
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