9.3.2 SCU Configuration Register

The SCU Configuration Register reads tag RAM sizes for the cores that are present, determines the cores that are taking part in coherency, and reads the number of cores present.

Usage constraints
This register is read-only.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x04

Reset value: IMPLEMENTATION DEFINED

The following figure shows the SCU Configuration Register bit assignments.

Figure 9-3 SCU Configuration Register bit assignments
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The following table shows the SCU Configuration Register bit assignments.

Table 9-4 SCU Configuration Register bit assignments

Bits Name Description
[31] M

This read-only bit indicates the inclusion of the AXI master port 1:

0b0AXI master port 1 not present.
0b1AXI master port 1 present.
[30:24] - Reserved. SBZ.
[23:20] Cache size for core 3

The encoding is as follows:

0b010164KB cache.
0b010032KB cache.
0b001116KB cache.
0b00108KB cache.
0b00014KB cache.
0b00000KB cache.

All other values are Reserved.

[19:16] Cache size for core 2

The encoding is as follows:

0b010164KB cache.
0b010032KB cache.
0b001116KB cache.
0b00108KB cache.
0b00014KB cache.
0b00000KB cache.

All other values are Reserved.

[15:12] Cache size for core 1

The encoding is as follows:

0b010164KB cache.
0b010032KB cache.
0b001116KB cache.
0b00108KB cache.
0b00014KB cache.
0b00000KB cache.

All other values are Reserved.

[11:8] Cache size for core 0

The encoding is as follows:

0b010164KB cache.
0b010032KB cache.
0b001116KB cache.
0b00108KB cache.
0b00014KB cache.
0b00000KB cache.

All other values are Reserved.

[7:4] Cores in coherency mode

Shows the cores that are in Symmetric Multiprocessing (SMP) or Asymmetric Multiprocessing (AMP) mode:

0b1This core is in SMP mode taking part in coherency.
0b0This core is in AMP mode not taking part in coherency or not present.
[7]
Core 3.
[6]
Core 2.
[5]
Core 1.
[4]
Core 0.
[3:2] - Reserved. SBZ.
[1:0] Number of cores

Number of cores present in the Cortex®‑R8 processor:

0b11Four cores, core 0, core 1, core 2 and core 3.
0b10Three cores, core 0, core 1 and core 2.
0b01Two cores, core 0 and core 1.
0b00One core, core 0.
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