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Instruction and data TCMs are tightly-coupled in the Cortex®‑R8 processor. There are no external ports for the TCMs and only SRAM memory is supported. Instructions cannot be stored in the Data TCM. An instruction fetch to the Data TCM goes to the AXI interface and not the Data TCM.
If an access corresponds to a TCM address, the access is treated as a cache hit and no other access is performed on the AXI buses.
There is an option to permit a single wait state on the instruction TCM. The data TCM does not accommodate wait states.
You can configure the instruction and data TCM size and the optional instruction TCM wait state during integration. See the ARM Cortex®‑R8 MPCore Processor Integration Manual for more information. The permissible TCM sizes are:
Both TCMs can be preloaded using the AXI TCM slave port. This slave port provides access to the TCMs only.
From the view of a programmer:
Both instruction and data TCM can be ECC protected.