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The processor L1 memory system can be configured during implementation and integration.
L1 memory system consists of:
Two optional TCM areas:
a configurable Data TCM (DTCM) from 0KB to 1024KB with no wait state support.
Each TCM and cache can be configured at implementation time to have an error detection and correction scheme to protect the data stored in the memory from errors. The TCMs are protected by ECC.
The MPU is unified, and handles accesses to both the instruction and data sides. The MPU is responsible for protection checking, address access permissions, and memory attributes. Some of these functions can be passed to the L2 memory system through the AXI master.
The L1 memory system includes a local monitor for exclusive
accesses. Exclusive load and store instructions can be used, for
the appropriate memory monitoring to provide inter-process or inter-processor
synchronization and semaphores. See the ARM® Architecture Reference
edition for more information.