B.3.3 Store multiple operations cycle timings

Details of the cycle timings of store multiple operations.

Table B-4 Store multiple operations cycle timings

Instruction AGU cycles
Aligned on a 64-bit boundary
Yes No
STM, {1 register} 1 1

STM, {2 registers}

STRD

SRS

1 2
STM, {3 registers} 2 2
STM, {4 registers} 2 3
STM, {5 registers} 3 3
STM, {6 registers} 3 4
STM, {7 registers} 4 4
STM, {8 registers} 4 5
STM, {9 registers} 5 5
STM, {10 registers} 5 6
STM, {11 registers} 6 6
STM, {12 registers} 6 7
STM, {13 registers} 7 7
STM, {14 registers} 7 8
STM, {15 registers} 8 8
STM, {16 registers} 8 9
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