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Coprocessor Access Control Register (CPACR) characteristics and bit assignments.
The following figure shows the CPACR bit assignments.
The following table shows the CPACR bit assignments.
Table 4-27 CPACR bit assignments
Defines access permissions for CP11:
Defines access permissions for CP10:
To access the CPACR, read or write the CP15 register with:
MRC p15, 0, <Rd>, c1, c0, 2 ; Read Coprocessor Access Control Register
MCR p15, 0, <Rd>, c1, c0, 2 ; Write Coprocessor Access Control Register
You must execute an
ISB immediately after
an update of the CPACR. See Memory Barriers in
the ARM® Architecture
edition. You must
not attempt to execute any instructions that are affected by the
change of access rights between the
ISB and the
To determine if any particular coprocessor exists in the system,
write the access bits for the coprocessor of interest with
If the coprocessor does not exist in the system the access rights
remain set to